[18/22] arm: [MVE intrinsics] factorize several binary_m operations
Commit Message
Factorize m-predicated versions of vabdq, vhaddq, vhsubq, vmaxq,
vminq, vmulhq, vqaddq, vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq,
vqdmulhq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq, vqrdmulhq,
vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq, vshlq
so that they use the same pattern.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MVE_INT_SU_M_BINARY): New.
(mve_insn): Add vabdq, vhaddq, vhsubq, vmaxq, vminq, vmulhq,
vqaddq, vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq, vqdmulhq,
vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq, vqrdmulhq,
vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq, vshlq.
(supf): Add VQDMLADHQ_M_S, VQDMLADHXQ_M_S, VQDMLSDHQ_M_S,
VQDMLSDHXQ_M_S, VQDMULHQ_M_S, VQRDMLADHQ_M_S, VQRDMLADHXQ_M_S,
VQRDMLSDHQ_M_S, VQRDMLSDHXQ_M_S, VQRDMULHQ_M_S.
* config/arm/mve.md (@mve_<mve_insn>q_m_<supf><mode>): New.
(mve_vshlq_m_<supf><mode>): Merged into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vabdq_m_<supf><mode>): Likewise.
(mve_vhaddq_m_<supf><mode>): Likewise.
(mve_vhsubq_m_<supf><mode>): Likewise.
(mve_vmaxq_m_<supf><mode>): Likewise.
(mve_vminq_m_<supf><mode>): Likewise.
(mve_vmulhq_m_<supf><mode>): Likewise.
(mve_vqaddq_m_<supf><mode>): Likewise.
(mve_vqrshlq_m_<supf><mode>): Likewise.
(mve_vqshlq_m_<supf><mode>): Likewise.
(mve_vqsubq_m_<supf><mode>): Likewise.
(mve_vrhaddq_m_<supf><mode>): Likewise.
(mve_vrmulhq_m_<supf><mode>): Likewise.
(mve_vrshlq_m_<supf><mode>): Likewise.
(mve_vqdmladhq_m_s<mode>): Likewise.
(mve_vqdmladhxq_m_s<mode>): Likewise.
(mve_vqdmlsdhq_m_s<mode>): Likewise.
(mve_vqdmlsdhxq_m_s<mode>): Likewise.
(mve_vqdmulhq_m_s<mode>): Likewise.
(mve_vqrdmladhq_m_s<mode>): Likewise.
(mve_vqrdmladhxq_m_s<mode>): Likewise.
(mve_vqrdmlsdhq_m_s<mode>): Likewise.
(mve_vqrdmlsdhxq_m_s<mode>): Likewise.
(mve_vqrdmulhq_m_s<mode>): Likewise.
---
gcc/config/arm/iterators.md | 65 +++++-
gcc/config/arm/mve.md | 420 +++---------------------------------
2 files changed, 91 insertions(+), 394 deletions(-)
Comments
> -----Original Message-----
> From: Christophe Lyon <christophe.lyon@arm.com>
> Sent: Tuesday, April 18, 2023 2:46 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
> Subject: [PATCH 18/22] arm: [MVE intrinsics] factorize several binary_m
> operations
>
> Factorize m-predicated versions of vabdq, vhaddq, vhsubq, vmaxq,
> vminq, vmulhq, vqaddq, vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq,
> vqdmulhq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq, vqrdmulhq,
> vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq, vshlq
> so that they use the same pattern.
>
> 2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
>
> gcc/
> * config/arm/iterators.md (MVE_INT_SU_M_BINARY): New.
> (mve_insn): Add vabdq, vhaddq, vhsubq, vmaxq, vminq, vmulhq,
> vqaddq, vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq,
> vqdmulhq,
> vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq, vqrdmulhq,
> vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq, vshlq.
> (supf): Add VQDMLADHQ_M_S, VQDMLADHXQ_M_S,
> VQDMLSDHQ_M_S,
> VQDMLSDHXQ_M_S, VQDMULHQ_M_S, VQRDMLADHQ_M_S,
> VQRDMLADHXQ_M_S,
> VQRDMLSDHQ_M_S, VQRDMLSDHXQ_M_S, VQRDMULHQ_M_S.
> * config/arm/mve.md (@mve_<mve_insn>q_m_<supf><mode>):
> New.
> (mve_vshlq_m_<supf><mode>): Merged into
> @mve_<mve_insn>q_m_<supf><mode>.
> (mve_vabdq_m_<supf><mode>): Likewise.
> (mve_vhaddq_m_<supf><mode>): Likewise.
> (mve_vhsubq_m_<supf><mode>): Likewise.
> (mve_vmaxq_m_<supf><mode>): Likewise.
> (mve_vminq_m_<supf><mode>): Likewise.
> (mve_vmulhq_m_<supf><mode>): Likewise.
> (mve_vqaddq_m_<supf><mode>): Likewise.
> (mve_vqrshlq_m_<supf><mode>): Likewise.
> (mve_vqshlq_m_<supf><mode>): Likewise.
> (mve_vqsubq_m_<supf><mode>): Likewise.
> (mve_vrhaddq_m_<supf><mode>): Likewise.
> (mve_vrmulhq_m_<supf><mode>): Likewise.
> (mve_vrshlq_m_<supf><mode>): Likewise.
> (mve_vqdmladhq_m_s<mode>): Likewise.
> (mve_vqdmladhxq_m_s<mode>): Likewise.
> (mve_vqdmlsdhq_m_s<mode>): Likewise.
> (mve_vqdmlsdhxq_m_s<mode>): Likewise.
> (mve_vqdmulhq_m_s<mode>): Likewise.
> (mve_vqrdmladhq_m_s<mode>): Likewise.
> (mve_vqrdmladhxq_m_s<mode>): Likewise.
> (mve_vqrdmlsdhq_m_s<mode>): Likewise.
> (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
> (mve_vqrdmulhq_m_s<mode>): Likewise.
> ---
> gcc/config/arm/iterators.md | 65 +++++-
> gcc/config/arm/mve.md | 420 +++---------------------------------
> 2 files changed, 91 insertions(+), 394 deletions(-)
>
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index 5a531d77a33..18d70350bbe 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -339,6 +339,33 @@ (define_int_iterator MVE_INT_M_BINARY [
> VSUBQ_M_S VSUBQ_M_U
> ])
>
> +(define_int_iterator MVE_INT_SU_M_BINARY [
> + VABDQ_M_S VABDQ_M_U
> + VHADDQ_M_S VHADDQ_M_U
> + VHSUBQ_M_S VHSUBQ_M_U
> + VMAXQ_M_S VMAXQ_M_U
> + VMINQ_M_S VMINQ_M_U
> + VMULHQ_M_S VMULHQ_M_U
> + VQADDQ_M_S VQADDQ_M_U
> + VQDMLADHQ_M_S
> + VQDMLADHXQ_M_S
> + VQDMLSDHQ_M_S
> + VQDMLSDHXQ_M_S
> + VQDMULHQ_M_S
> + VQRDMLADHQ_M_S
> + VQRDMLADHXQ_M_S
> + VQRDMLSDHQ_M_S
> + VQRDMLSDHXQ_M_S
> + VQRDMULHQ_M_S
> + VQRSHLQ_M_S VQRSHLQ_M_U
> + VQSHLQ_M_S VQSHLQ_M_U
> + VQSUBQ_M_S VQSUBQ_M_U
> + VRHADDQ_M_S VRHADDQ_M_U
> + VRMULHQ_M_S VRMULHQ_M_U
> + VRSHLQ_M_S VRSHLQ_M_U
> + VSHLQ_M_S VSHLQ_M_U
> + ])
> +
> (define_int_iterator MVE_INT_M_BINARY_LOGIC [
> VANDQ_M_S VANDQ_M_U
> VBICQ_M_S VBICQ_M_U
> @@ -404,6 +431,7 @@ (define_code_attr mve_addsubmul [
> ])
>
> (define_int_attr mve_insn [
> + (VABDQ_M_S "vabd") (VABDQ_M_U "vabd")
> (VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd")
> (VADDQ_M_N_F "vadd")
> (VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F
> "vadd")
> (VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F
> "vadd")
> @@ -413,12 +441,35 @@ (define_int_attr mve_insn [
> (VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
> (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate")
> (VCREATEQ_F "vcreate")
> (VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F
> "veor")
> + (VHADDQ_M_S "vhadd") (VHADDQ_M_U "vhadd")
> + (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
> + (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
> + (VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
> + (VMULHQ_M_S "vmulh") (VMULHQ_M_U "vmulh")
> (VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul")
> (VMULQ_M_N_F "vmul")
> (VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F
> "vmul")
> (VMULQ_N_S "vmul") (VMULQ_N_U "vmul") (VMULQ_N_F
> "vmul")
> (VORRQ_M_N_S "vorr") (VORRQ_M_N_U "vorr")
> (VORRQ_M_S "vorr") (VORRQ_M_U "vorr") (VORRQ_M_F
> "vorr")
> (VORRQ_N_S "vorr") (VORRQ_N_U "vorr")
> + (VQADDQ_M_S "vqadd") (VQADDQ_M_U "vqadd")
> + (VQDMLADHQ_M_S "vqdmladh")
> + (VQDMLADHXQ_M_S "vqdmladhx")
> + (VQDMLSDHQ_M_S "vqdmlsdh")
> + (VQDMLSDHXQ_M_S "vqdmlsdhx")
> + (VQDMULHQ_M_S "vqdmulh")
> + (VQRDMLADHQ_M_S "vqrdmladh")
> + (VQRDMLADHXQ_M_S "vqrdmladhx")
> + (VQRDMLSDHQ_M_S "vqrdmlsdh")
> + (VQRDMLSDHXQ_M_S "vqrdmlsdhx")
> + (VQRDMULHQ_M_S "vqrdmulh")
> + (VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl")
> + (VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl")
> + (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub")
> + (VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd")
> + (VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh")
> + (VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl")
> + (VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl")
> (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub")
> (VSUBQ_M_N_F "vsub")
> (VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F
> "vsub")
> (VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F
> "vsub")
> @@ -1557,7 +1608,19 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s")
> (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
> (VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s")
> (VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48")
> (UQRSHLL_64 "64") (UQRSHLL_48 "48") (VSHLCQ_M_S
> "s")
> - (VSHLCQ_M_U "u")])
> + (VSHLCQ_M_U "u")
> + (VQDMLADHQ_M_S "s")
> + (VQDMLADHXQ_M_S "s")
> + (VQDMLSDHQ_M_S "s")
> + (VQDMLSDHXQ_M_S "s")
> + (VQDMULHQ_M_S "s")
> + (VQRDMLADHQ_M_S "s")
> + (VQRDMLADHXQ_M_S "s")
> + (VQRDMLSDHQ_M_S "s")
> + (VQRDMLSDHXQ_M_S "s")
> + (VQRDMULHQ_M_S "s")
> + ])
> +
> ;; Both kinds of return insn.
> (define_code_iterator RETURNS [return simple_return])
> (define_code_attr return_str [(return "") (simple_return "simple_")])
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index f7f0ba65251..21c54197db5 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -4867,23 +4867,6 @@ (define_insn "mve_vqshluq_m_n_s<mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length" "8")])
>
> -;;
> -;; [vshlq_m_s, vshlq_m_u])
> -;;
> -(define_insn "mve_vshlq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VSHLQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length" "8")])
> -
> ;;
> ;; [vsriq_m_n_s, vsriq_m_n_u])
> ;;
> @@ -4917,20 +4900,44 @@ (define_insn
> "mve_vcvtq_m_n_to_f_<supf><mode>"
> "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
> +
> ;;
> ;; [vabdq_m_s, vabdq_m_u])
> +;; [vhaddq_m_s, vhaddq_m_u])
> +;; [vhsubq_m_s, vhsubq_m_u])
> +;; [vmaxq_m_s, vmaxq_m_u])
> +;; [vminq_m_s, vminq_m_u])
> +;; [vmulhq_m_s, vmulhq_m_u])
> +;; [vqaddq_m_u, vqaddq_m_s])
> +;; [vqdmladhq_m_s])
> +;; [vqdmladhxq_m_s])
> +;; [vqdmlsdhq_m_s])
> +;; [vqdmlsdhxq_m_s])
> +;; [vqdmulhq_m_s])
> +;; [vqrdmladhq_m_s])
> +;; [vqrdmladhxq_m_s])
> +;; [vqrdmlsdhq_m_s])
> +;; [vqrdmlsdhxq_m_s])
> +;; [vqrdmulhq_m_s])
> +;; [vqrshlq_m_u, vqrshlq_m_s])
> +;; [vqshlq_m_u, vqshlq_m_s])
> +;; [vqsubq_m_u, vqsubq_m_s])
> +;; [vrhaddq_m_u, vrhaddq_m_s])
> +;; [vrmulhq_m_u, vrmulhq_m_s])
> +;; [vrshlq_m_s, vrshlq_m_u])
> +;; [vshlq_m_s, vshlq_m_u])
Ok with the trailing ')' removed.
Thanks,
Kyrill
> ;;
> -(define_insn "mve_vabdq_m_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
> [
> (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> (match_operand:MVE_2 2 "s_register_operand" "w")
> (match_operand:MVE_2 3 "s_register_operand" "w")
> (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VABDQ_M))
> + MVE_INT_SU_M_BINARY))
> ]
> "TARGET_HAVE_MVE"
> - "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
> + "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> @@ -5060,23 +5067,6 @@ (define_insn "mve_vhaddq_m_n_<supf><mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vhaddq_m_s, vhaddq_m_u])
> -;;
> -(define_insn "mve_vhaddq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VHADDQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vhsubq_m_n_s, vhsubq_m_n_u])
> ;;
> @@ -5095,56 +5085,6 @@ (define_insn "mve_vhsubq_m_n_<supf><mode>"
> (set_attr "length""8")])
>
> ;;
> -;; [vhsubq_m_s, vhsubq_m_u])
> -;;
> -(define_insn "mve_vhsubq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VHSUBQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vmaxq_m_s, vmaxq_m_u])
> -;;
> -(define_insn "mve_vmaxq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VMAXQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vminq_m_s, vminq_m_u])
> -;;
> -(define_insn "mve_vminq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VMINQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vmladavaq_p_u, vmladavaq_p_s])
> ;;
> @@ -5196,23 +5136,6 @@ (define_insn "mve_vmlasq_m_n_<supf><mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vmulhq_m_s, vmulhq_m_u])
> -;;
> -(define_insn "mve_vmulhq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VMULHQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vmullbq_int_m_u, vmullbq_int_m_s])
> ;;
> @@ -5281,23 +5204,6 @@ (define_insn "mve_vqaddq_m_n_<supf><mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vqaddq_m_u, vqaddq_m_s])
> -;;
> -(define_insn "mve_vqaddq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQADDQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vqdmlahq_m_n_s])
> ;;
> @@ -5366,23 +5272,6 @@ (define_insn "mve_vqrdmlashq_m_n_s<mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vqrshlq_m_u, vqrshlq_m_s])
> -;;
> -(define_insn "mve_vqrshlq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQRSHLQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vqshlq_m_n_s, vqshlq_m_n_u])
> ;;
> @@ -5400,23 +5289,6 @@ (define_insn "mve_vqshlq_m_n_<supf><mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vqshlq_m_u, vqshlq_m_s])
> -;;
> -(define_insn "mve_vqshlq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQSHLQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vqsubq_m_n_u, vqsubq_m_n_s])
> ;;
> @@ -5434,74 +5306,6 @@ (define_insn "mve_vqsubq_m_n_<supf><mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vqsubq_m_u, vqsubq_m_s])
> -;;
> -(define_insn "mve_vqsubq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQSUBQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vrhaddq_m_u, vrhaddq_m_s])
> -;;
> -(define_insn "mve_vrhaddq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VRHADDQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vrmulhq_m_u, vrmulhq_m_s])
> -;;
> -(define_insn "mve_vrmulhq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VRMULHQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vrshlq_m_s, vrshlq_m_u])
> -;;
> -(define_insn "mve_vrshlq_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VRSHLQ_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vrshrq_m_n_s, vrshrq_m_n_u])
> ;;
> @@ -5655,74 +5459,6 @@ (define_insn "mve_vmlsdavaxq_p_s<mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vqdmladhq_m_s])
> -;;
> -(define_insn "mve_vqdmladhq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQDMLADHQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vqdmladhxq_m_s])
> -;;
> -(define_insn "mve_vqdmladhxq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQDMLADHXQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vqdmlsdhq_m_s])
> -;;
> -(define_insn "mve_vqdmlsdhq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQDMLSDHQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vqdmlsdhxq_m_s])
> -;;
> -(define_insn "mve_vqdmlsdhxq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQDMLSDHXQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vqdmulhq_m_n_s])
> ;;
> @@ -5740,91 +5476,6 @@ (define_insn "mve_vqdmulhq_m_n_s<mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vqdmulhq_m_s])
> -;;
> -(define_insn "mve_vqdmulhq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQDMULHQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vqrdmladhq_m_s])
> -;;
> -(define_insn "mve_vqrdmladhq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQRDMLADHQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vqrdmladhxq_m_s])
> -;;
> -(define_insn "mve_vqrdmladhxq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQRDMLADHXQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vqrdmlsdhq_m_s])
> -;;
> -(define_insn "mve_vqrdmlsdhq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQRDMLSDHQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vqrdmlsdhxq_m_s])
> -;;
> -(define_insn "mve_vqrdmlsdhxq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQRDMLSDHXQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vqrdmulhq_m_n_s])
> ;;
> @@ -5842,23 +5493,6 @@ (define_insn "mve_vqrdmulhq_m_n_s<mode>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vqrdmulhq_m_s])
> -;;
> -(define_insn "mve_vqrdmulhq_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VQRDMULHQ_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vmlaldavaq_p_u, vmlaldavaq_p_s])
> ;;
> --
> 2.34.1
@@ -339,6 +339,33 @@ (define_int_iterator MVE_INT_M_BINARY [
VSUBQ_M_S VSUBQ_M_U
])
+(define_int_iterator MVE_INT_SU_M_BINARY [
+ VABDQ_M_S VABDQ_M_U
+ VHADDQ_M_S VHADDQ_M_U
+ VHSUBQ_M_S VHSUBQ_M_U
+ VMAXQ_M_S VMAXQ_M_U
+ VMINQ_M_S VMINQ_M_U
+ VMULHQ_M_S VMULHQ_M_U
+ VQADDQ_M_S VQADDQ_M_U
+ VQDMLADHQ_M_S
+ VQDMLADHXQ_M_S
+ VQDMLSDHQ_M_S
+ VQDMLSDHXQ_M_S
+ VQDMULHQ_M_S
+ VQRDMLADHQ_M_S
+ VQRDMLADHXQ_M_S
+ VQRDMLSDHQ_M_S
+ VQRDMLSDHXQ_M_S
+ VQRDMULHQ_M_S
+ VQRSHLQ_M_S VQRSHLQ_M_U
+ VQSHLQ_M_S VQSHLQ_M_U
+ VQSUBQ_M_S VQSUBQ_M_U
+ VRHADDQ_M_S VRHADDQ_M_U
+ VRMULHQ_M_S VRMULHQ_M_U
+ VRSHLQ_M_S VRSHLQ_M_U
+ VSHLQ_M_S VSHLQ_M_U
+ ])
+
(define_int_iterator MVE_INT_M_BINARY_LOGIC [
VANDQ_M_S VANDQ_M_U
VBICQ_M_S VBICQ_M_U
@@ -404,6 +431,7 @@ (define_code_attr mve_addsubmul [
])
(define_int_attr mve_insn [
+ (VABDQ_M_S "vabd") (VABDQ_M_U "vabd")
(VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd") (VADDQ_M_N_F "vadd")
(VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F "vadd")
(VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F "vadd")
@@ -413,12 +441,35 @@ (define_int_attr mve_insn [
(VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
(VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate")
(VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor")
+ (VHADDQ_M_S "vhadd") (VHADDQ_M_U "vhadd")
+ (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
+ (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
+ (VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
+ (VMULHQ_M_S "vmulh") (VMULHQ_M_U "vmulh")
(VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") (VMULQ_M_N_F "vmul")
(VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F "vmul")
(VMULQ_N_S "vmul") (VMULQ_N_U "vmul") (VMULQ_N_F "vmul")
(VORRQ_M_N_S "vorr") (VORRQ_M_N_U "vorr")
(VORRQ_M_S "vorr") (VORRQ_M_U "vorr") (VORRQ_M_F "vorr")
(VORRQ_N_S "vorr") (VORRQ_N_U "vorr")
+ (VQADDQ_M_S "vqadd") (VQADDQ_M_U "vqadd")
+ (VQDMLADHQ_M_S "vqdmladh")
+ (VQDMLADHXQ_M_S "vqdmladhx")
+ (VQDMLSDHQ_M_S "vqdmlsdh")
+ (VQDMLSDHXQ_M_S "vqdmlsdhx")
+ (VQDMULHQ_M_S "vqdmulh")
+ (VQRDMLADHQ_M_S "vqrdmladh")
+ (VQRDMLADHXQ_M_S "vqrdmladhx")
+ (VQRDMLSDHQ_M_S "vqrdmlsdh")
+ (VQRDMLSDHXQ_M_S "vqrdmlsdhx")
+ (VQRDMULHQ_M_S "vqrdmulh")
+ (VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl")
+ (VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl")
+ (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub")
+ (VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd")
+ (VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh")
+ (VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl")
+ (VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl")
(VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
(VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
(VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")
@@ -1557,7 +1608,19 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
(VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s")
(VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48")
(UQRSHLL_64 "64") (UQRSHLL_48 "48") (VSHLCQ_M_S "s")
- (VSHLCQ_M_U "u")])
+ (VSHLCQ_M_U "u")
+ (VQDMLADHQ_M_S "s")
+ (VQDMLADHXQ_M_S "s")
+ (VQDMLSDHQ_M_S "s")
+ (VQDMLSDHXQ_M_S "s")
+ (VQDMULHQ_M_S "s")
+ (VQRDMLADHQ_M_S "s")
+ (VQRDMLADHXQ_M_S "s")
+ (VQRDMLSDHQ_M_S "s")
+ (VQRDMLSDHXQ_M_S "s")
+ (VQRDMULHQ_M_S "s")
+ ])
+
;; Both kinds of return insn.
(define_code_iterator RETURNS [return simple_return])
(define_code_attr return_str [(return "") (simple_return "simple_")])
@@ -4867,23 +4867,6 @@ (define_insn "mve_vqshluq_m_n_s<mode>"
[(set_attr "type" "mve_move")
(set_attr "length" "8")])
-;;
-;; [vshlq_m_s, vshlq_m_u])
-;;
-(define_insn "mve_vshlq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VSHLQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length" "8")])
-
;;
;; [vsriq_m_n_s, vsriq_m_n_u])
;;
@@ -4917,20 +4900,44 @@ (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
"vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
+
;;
;; [vabdq_m_s, vabdq_m_u])
+;; [vhaddq_m_s, vhaddq_m_u])
+;; [vhsubq_m_s, vhsubq_m_u])
+;; [vmaxq_m_s, vmaxq_m_u])
+;; [vminq_m_s, vminq_m_u])
+;; [vmulhq_m_s, vmulhq_m_u])
+;; [vqaddq_m_u, vqaddq_m_s])
+;; [vqdmladhq_m_s])
+;; [vqdmladhxq_m_s])
+;; [vqdmlsdhq_m_s])
+;; [vqdmlsdhxq_m_s])
+;; [vqdmulhq_m_s])
+;; [vqrdmladhq_m_s])
+;; [vqrdmladhxq_m_s])
+;; [vqrdmlsdhq_m_s])
+;; [vqrdmlsdhxq_m_s])
+;; [vqrdmulhq_m_s])
+;; [vqrshlq_m_u, vqrshlq_m_s])
+;; [vqshlq_m_u, vqshlq_m_s])
+;; [vqsubq_m_u, vqsubq_m_s])
+;; [vrhaddq_m_u, vrhaddq_m_s])
+;; [vrmulhq_m_u, vrmulhq_m_s])
+;; [vrshlq_m_s, vrshlq_m_u])
+;; [vshlq_m_s, vshlq_m_u])
;;
-(define_insn "mve_vabdq_m_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VABDQ_M))
+ MVE_INT_SU_M_BINARY))
]
"TARGET_HAVE_MVE"
- "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5060,23 +5067,6 @@ (define_insn "mve_vhaddq_m_n_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vhaddq_m_s, vhaddq_m_u])
-;;
-(define_insn "mve_vhaddq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VHADDQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vhsubq_m_n_s, vhsubq_m_n_u])
;;
@@ -5095,56 +5085,6 @@ (define_insn "mve_vhsubq_m_n_<supf><mode>"
(set_attr "length""8")])
;;
-;; [vhsubq_m_s, vhsubq_m_u])
-;;
-(define_insn "mve_vhsubq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VHSUBQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vmaxq_m_s, vmaxq_m_u])
-;;
-(define_insn "mve_vmaxq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VMAXQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vminq_m_s, vminq_m_u])
-;;
-(define_insn "mve_vminq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VMINQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vmladavaq_p_u, vmladavaq_p_s])
;;
@@ -5196,23 +5136,6 @@ (define_insn "mve_vmlasq_m_n_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vmulhq_m_s, vmulhq_m_u])
-;;
-(define_insn "mve_vmulhq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VMULHQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vmullbq_int_m_u, vmullbq_int_m_s])
;;
@@ -5281,23 +5204,6 @@ (define_insn "mve_vqaddq_m_n_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vqaddq_m_u, vqaddq_m_s])
-;;
-(define_insn "mve_vqaddq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQADDQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vqdmlahq_m_n_s])
;;
@@ -5366,23 +5272,6 @@ (define_insn "mve_vqrdmlashq_m_n_s<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vqrshlq_m_u, vqrshlq_m_s])
-;;
-(define_insn "mve_vqrshlq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQRSHLQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vqshlq_m_n_s, vqshlq_m_n_u])
;;
@@ -5400,23 +5289,6 @@ (define_insn "mve_vqshlq_m_n_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vqshlq_m_u, vqshlq_m_s])
-;;
-(define_insn "mve_vqshlq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQSHLQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vqsubq_m_n_u, vqsubq_m_n_s])
;;
@@ -5434,74 +5306,6 @@ (define_insn "mve_vqsubq_m_n_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vqsubq_m_u, vqsubq_m_s])
-;;
-(define_insn "mve_vqsubq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQSUBQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrhaddq_m_u, vrhaddq_m_s])
-;;
-(define_insn "mve_vrhaddq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VRHADDQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrmulhq_m_u, vrmulhq_m_s])
-;;
-(define_insn "mve_vrmulhq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VRMULHQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrshlq_m_s, vrshlq_m_u])
-;;
-(define_insn "mve_vrshlq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VRSHLQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vrshrq_m_n_s, vrshrq_m_n_u])
;;
@@ -5655,74 +5459,6 @@ (define_insn "mve_vmlsdavaxq_p_s<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vqdmladhq_m_s])
-;;
-(define_insn "mve_vqdmladhq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQDMLADHQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqdmladhxq_m_s])
-;;
-(define_insn "mve_vqdmladhxq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQDMLADHXQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqdmlsdhq_m_s])
-;;
-(define_insn "mve_vqdmlsdhq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQDMLSDHQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqdmlsdhxq_m_s])
-;;
-(define_insn "mve_vqdmlsdhxq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQDMLSDHXQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vqdmulhq_m_n_s])
;;
@@ -5740,91 +5476,6 @@ (define_insn "mve_vqdmulhq_m_n_s<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vqdmulhq_m_s])
-;;
-(define_insn "mve_vqdmulhq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQDMULHQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqrdmladhq_m_s])
-;;
-(define_insn "mve_vqrdmladhq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQRDMLADHQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqrdmladhxq_m_s])
-;;
-(define_insn "mve_vqrdmladhxq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQRDMLADHXQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqrdmlsdhq_m_s])
-;;
-(define_insn "mve_vqrdmlsdhq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQRDMLSDHQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vqrdmlsdhxq_m_s])
-;;
-(define_insn "mve_vqrdmlsdhxq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQRDMLSDHXQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vqrdmulhq_m_n_s])
;;
@@ -5842,23 +5493,6 @@ (define_insn "mve_vqrdmulhq_m_n_s<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vqrdmulhq_m_s])
-;;
-(define_insn "mve_vqrdmulhq_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VQRDMULHQ_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vmlaldavaq_p_u, vmlaldavaq_p_s])
;;