| Message ID | 20230418134608.244751-17-christophe.lyon@arm.com |
|---|---|
| State | Committed |
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To: <gcc-patches@gcc.gnu.org>, <kyrylo.tkachov@arm.com>,
<richard.earnshaw@arm.com>, <richard.sandiford@arm.com>
CC: Christophe Lyon <christophe.lyon@arm.com>
Subject: [PATCH 16/22] arm: [MVE intrinsics] factorize vcreateq
Date: Tue, 18 Apr 2023 15:46:02 +0200
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|
| Series |
arm: New framework for MVE intrinsics
|
|
Commit Message
Christophe Lyon
April 18, 2023, 1:46 p.m. UTC
We need a 'fake' iterator to be able to use mve_insn for vcreateq_f. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_FP_CREATE): New. (mve_insn): Add VCREATEQ_S, VCREATEQ_U, VCREATEQ_F. * config/arm/mve.md (mve_vcreateq_f<mode>): Rename into ... (@mve_<mve_insn>q_f<mode>): ... this. (mve_vcreateq_<supf><mode>): Rename into ... (@mve_<mve_insn>q_<supf><mode>): ... this. --- gcc/config/arm/iterators.md | 5 +++++ gcc/config/arm/mve.md | 6 +++--- 2 files changed, 8 insertions(+), 3 deletions(-)
Comments
> -----Original Message----- > From: Christophe Lyon <christophe.lyon@arm.com> > Sent: Tuesday, April 18, 2023 2:46 PM > To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; > Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford > <Richard.Sandiford@arm.com> > Cc: Christophe Lyon <Christophe.Lyon@arm.com> > Subject: [PATCH 16/22] arm: [MVE intrinsics] factorize vcreateq > > We need a 'fake' iterator to be able to use mve_insn for vcreateq_f. > > 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> > > gcc/ > * config/arm/iterators.md (MVE_FP_CREATE): New. > (mve_insn): Add VCREATEQ_S, VCREATEQ_U, VCREATEQ_F. > * config/arm/mve.md (mve_vcreateq_f<mode>): Rename into ... > (@mve_<mve_insn>q_f<mode>): ... this. > (mve_vcreateq_<supf><mode>): Rename into ... > (@mve_<mve_insn>q_<supf><mode>): ... this. > --- > gcc/config/arm/iterators.md | 5 +++++ > gcc/config/arm/mve.md | 6 +++--- > 2 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md > index b0ea1af77d2..5a531d77a33 100644 > --- a/gcc/config/arm/iterators.md > +++ b/gcc/config/arm/iterators.md > @@ -393,6 +393,10 @@ (define_int_iterator MVE_FP_N_BINARY [ > VSUBQ_N_F > ]) > > +(define_int_iterator MVE_FP_CREATE [ > + VCREATEQ_F > + ]) I believe in similar cases in the aarch64 port we used the convention "ONLY", so something like VCREATEQ_F_ONLY. Ok with that change. Thanks, Kyrill > + > (define_code_attr mve_addsubmul [ > (minus "vsub") > (mult "vmul") > @@ -407,6 +411,7 @@ (define_int_attr mve_insn [ > (VBICQ_M_N_S "vbic") (VBICQ_M_N_U "vbic") > (VBICQ_M_S "vbic") (VBICQ_M_U "vbic") (VBICQ_M_F > "vbic") > (VBICQ_N_S "vbic") (VBICQ_N_U "vbic") > + (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") > (VCREATEQ_F "vcreate") > (VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F > "veor") > (VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") > (VMULQ_M_N_F "vmul") > (VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F > "vmul") > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index fbae1d3791f..f7f0ba65251 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -700,12 +700,12 @@ (define_insn "mve_vcvtq_n_to_f_<supf><mode>" > > ;; [vcreateq_f]) > ;; > -(define_insn "mve_vcreateq_f<mode>" > +(define_insn "@mve_<mve_insn>q_f<mode>" > [ > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r") > (match_operand:DI 2 "s_register_operand" "r")] > - VCREATEQ_F)) > + MVE_FP_CREATE)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2" > @@ -715,7 +715,7 @@ (define_insn "mve_vcreateq_f<mode>" > ;; > ;; [vcreateq_u, vcreateq_s]) > ;; > -(define_insn "mve_vcreateq_<supf><mode>" > +(define_insn "@mve_<mve_insn>q_<supf><mode>" > [ > (set (match_operand:MVE_1 0 "s_register_operand" "=w") > (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r") > -- > 2.34.1
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index b0ea1af77d2..5a531d77a33 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -393,6 +393,10 @@ (define_int_iterator MVE_FP_N_BINARY [ VSUBQ_N_F ]) +(define_int_iterator MVE_FP_CREATE [ + VCREATEQ_F + ]) + (define_code_attr mve_addsubmul [ (minus "vsub") (mult "vmul") @@ -407,6 +411,7 @@ (define_int_attr mve_insn [ (VBICQ_M_N_S "vbic") (VBICQ_M_N_U "vbic") (VBICQ_M_S "vbic") (VBICQ_M_U "vbic") (VBICQ_M_F "vbic") (VBICQ_N_S "vbic") (VBICQ_N_U "vbic") + (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate") (VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor") (VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") (VMULQ_M_N_F "vmul") (VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F "vmul") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index fbae1d3791f..f7f0ba65251 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -700,12 +700,12 @@ (define_insn "mve_vcvtq_n_to_f_<supf><mode>" ;; [vcreateq_f]) ;; -(define_insn "mve_vcreateq_f<mode>" +(define_insn "@mve_<mve_insn>q_f<mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r") (match_operand:DI 2 "s_register_operand" "r")] - VCREATEQ_F)) + MVE_FP_CREATE)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2" @@ -715,7 +715,7 @@ (define_insn "mve_vcreateq_f<mode>" ;; ;; [vcreateq_u, vcreateq_s]) ;; -(define_insn "mve_vcreateq_<supf><mode>" +(define_insn "@mve_<mve_insn>q_<supf><mode>" [ (set (match_operand:MVE_1 0 "s_register_operand" "=w") (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")