[4/9] rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p4
Commit Message
All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.
This is part 4, it further checks for comparison opeators
LT/UNGE. In rs6000_emit_vector_compare, for the handling
of LT, it switches to use code GT, swaps operands and try
again, it's exactly the same as what we have in vector.md:
; lt(a,b) = gt(b,a)
As to UNGE, in rs6000_emit_vector_compare, it uses reversed
code LT and further operates on the result with one_cmpl,
it's also the same as what's in vector.md:
; unge(a,b) = ~lt(a,b)
This patch should not have any functionality change too.
gcc/ChangeLog:
* config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Emit rtx
comparison for operators LT/UNGE of MODE_VECTOR_FLOAT directly.
(rs6000_emit_vector_compare): Move assertion of no MODE_VECTOR_FLOAT to
function beginning.
---
gcc/config/rs6000/rs6000.cc | 24 ++++--------------------
1 file changed, 4 insertions(+), 20 deletions(-)
@@ -15645,6 +15645,7 @@ static rtx
rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
{
machine_mode mode = GET_MODE (op0);
+ gcc_assert (GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT);
switch (code)
{
@@ -15654,7 +15655,6 @@ rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
case EQ:
case GT:
case GTU:
- gcc_assert (GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT);
rtx mask = gen_reg_rtx (mode);
emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
return mask;
@@ -15679,18 +15679,8 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
comparison operators in a comparison rtl pattern, we can
just emit the comparison rtx insn directly here. Besides,
we should have a centralized place to handle the possibility
- of raising invalid exception. For EQ/GT/GE/UNORDERED/
- ORDERED/LTGT/UNEQ, they are handled equivalently as before;
- for NE/UNLE/UNLT, they are handled with reversed code
- and inverting, it's the same as before; for LE/UNGT, they
- are handled with LE ior EQ previously, emitting directly
- here will make use of GE later, it's slightly better;
-
- FIXME: Handle the remaining vector float comparison operators
- here. */
- if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT
- && rcode != LT
- && rcode != UNGE)
+ of raising invalid exception. */
+ if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT)
{
mask = gen_reg_rtx (dmode);
emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
@@ -15718,23 +15708,17 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
try_again = true;
break;
case NE:
- case UNGE:
/* Invert condition and try again.
e.g., A != B becomes ~(A==B). */
{
- enum rtx_code rev_code;
enum insn_code nor_code;
rtx mask2;
- rev_code = reverse_condition_maybe_unordered (rcode);
- if (rev_code == UNKNOWN)
- return NULL_RTX;
-
nor_code = optab_handler (one_cmpl_optab, dmode);
if (nor_code == CODE_FOR_nothing)
return NULL_RTX;
- mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
+ mask2 = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
if (!mask2)
return NULL_RTX;