[3/9] rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p3
Commit Message
All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.
This is part 3, it further checks for comparison opeators
LE/UNGT. In rs6000_emit_vector_compare, UNGT is handled
with reversed code LE and inverting with one_cmpl_optab,
LE is handled with LT ior EQ, while in vector.md, we have
the support:
; le(a,b) = ge(b,a)
; ungt(a,b) = ~le(a,b)
The associated test case shows it's an improvement.
gcc/ChangeLog:
* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Emit rtx
comparison for operators LE/UNGT of MODE_VECTOR_FLOAT directly.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/vcond-fp.c: New test.
---
gcc/config/rs6000/rs6000.cc | 9 ++++----
gcc/testsuite/gcc.target/powerpc/vcond-fp.c | 25 +++++++++++++++++++++
2 files changed, 29 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/vcond-fp.c
@@ -15682,15 +15682,15 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
of raising invalid exception. For EQ/GT/GE/UNORDERED/
ORDERED/LTGT/UNEQ, they are handled equivalently as before;
for NE/UNLE/UNLT, they are handled with reversed code
- and inverting, it's the same as before.
+ and inverting, it's the same as before; for LE/UNGT, they
+ are handled with LE ior EQ previously, emitting directly
+ here will make use of GE later, it's slightly better;
FIXME: Handle the remaining vector float comparison operators
here. */
if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT
&& rcode != LT
- && rcode != LE
- && rcode != UNGE
- && rcode != UNGT)
+ && rcode != UNGE)
{
mask = gen_reg_rtx (dmode);
emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
@@ -15719,7 +15719,6 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
break;
case NE:
case UNGE:
- case UNGT:
/* Invert condition and try again.
e.g., A != B becomes ~(A==B). */
{
new file mode 100644
@@ -0,0 +1,25 @@
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model -mpower8-vector" } */
+
+/* Test we use xvcmpge[sd]p rather than xvcmpeq[sd]p and xvcmpgt[sd]p
+ for UNGT and LE handlings. */
+
+#define UNGT(a, b) (!__builtin_islessequal ((a), (b)))
+#define LE(a, b) (((a) <= (b)))
+
+#define TEST_VECT(NAME, TYPE) \
+ __attribute__ ((noipa)) void test_##NAME##_##TYPE (TYPE *x, TYPE *y, \
+ int *res, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ res[i] = NAME (x[i], y[i]); \
+ }
+
+#define TEST(TYPE) \
+ TEST_VECT (UNGT, TYPE) \
+ TEST_VECT (LE, TYPE)
+
+TEST (float)
+TEST (double)
+
+/* { dg-final { scan-assembler-not {\mxvcmp(gt|eq)[sd]p\M} } } */