This is the change to which I alluded to this in r11-220 /
d0780379c1b6 as "causes extra register moves in libgcc". It has
unfortunate side-effects due to the change in register-class topology.
There's a slight improvement in coremark numbers (< 0.07%) though also
increase in code size total (< 0.7%) but looking at the individual
changes in functions, it's all-over (-7..+7%). Looking specifically
at functions that improved in speed, it's also both plus and minus in
code sizes. It's unworkable to separate improvements from regressions
for this case. I'll follow up with patches to restore the previous
code quality, in both size and speed.
gcc:
* config/cris/constraints.md (define_register_constraint "b"): Now
GENERAL_REGS.
* config/cris/cris.md (CRIS_ACR_REGNUM): Remove.
* config/cris/cris.h: (reg_class, REG_CLASS_NAMES)
(REG_CLASS_CONTENTS): Remove ACR_REGS, SPEC_ACR_REGS, GENNONACR_REGS,
and SPEC_GENNONACR_REGS.
* config/cris/cris.cc (cris_preferred_reload_class): Don't mention
ACR_REGS and return GENERAL_REGS instead of GENNONACR_REGS.
---
gcc/config/cris/constraints.md | 7 ++++++-
gcc/config/cris/cris.cc | 5 ++---
gcc/config/cris/cris.h | 27 +++++----------------------
gcc/config/cris/cris.md | 1 -
4 files changed, 13 insertions(+), 27 deletions(-)
@@ -18,7 +18,12 @@
;; <http://www.gnu.org/licenses/>.
;; Register constraints.
-(define_register_constraint "b" "GENNONACR_REGS"
+
+;; Kept for compatibility. It used to exclude the CRIS v32
+;; register "ACR", which was like GENERAL_REGS except it
+;; couldn't be used for autoincrement, and intended mainly
+;; for use in user asm statements.
+(define_register_constraint "b" "GENERAL_REGS"
"@internal")
(define_register_constraint "h" "MOF_REGS"
@@ -1663,13 +1663,12 @@ cris_reload_address_legitimized (rtx x,
static reg_class_t
cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass)
{
- if (rclass != ACR_REGS
- && rclass != MOF_REGS
+ if (rclass != MOF_REGS
&& rclass != MOF_SRP_REGS
&& rclass != SRP_REGS
&& rclass != CC0_REGS
&& rclass != SPECIAL_REGS)
- return GENNONACR_REGS;
+ return GENERAL_REGS;
return rclass;
}
@@ -436,19 +436,15 @@ extern int cris_cpu_version;
/* Node: Register Classes */
-/* We need a separate register class to handle register allocation for
- ACR, since it can't be used for post-increment.
-
- It's not obvious, but having subunions of all movable-between
+/* It's not obvious, but having subunions of all movable-between
register classes does really help register allocation (pre-IRA
comment). */
enum reg_class
{
NO_REGS,
- ACR_REGS, MOF_REGS, SRP_REGS, CC0_REGS,
+ MOF_REGS, SRP_REGS, CC0_REGS,
MOF_SRP_REGS, SPECIAL_REGS,
- SPEC_ACR_REGS, GENNONACR_REGS,
- SPEC_GENNONACR_REGS, GENERAL_REGS,
+ GENERAL_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -457,9 +453,8 @@ enum reg_class
#define REG_CLASS_NAMES \
{"NO_REGS", \
- "ACR_REGS", "MOF_REGS", "SRP_REGS", "CC0_REGS", \
+ "MOF_REGS", "SRP_REGS", "CC0_REGS", \
"MOF_SRP_REGS", "SPECIAL_REGS", \
- "SPEC_ACR_REGS", "GENNONACR_REGS", "SPEC_GENNONACR_REGS", \
"GENERAL_REGS", "ALL_REGS"}
#define CRIS_SPECIAL_REGS_CONTENTS \
@@ -472,37 +467,25 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ \
{0}, \
- {1 << CRIS_ACR_REGNUM}, \
{1 << CRIS_MOF_REGNUM}, \
{1 << CRIS_SRP_REGNUM}, \
{1 << CRIS_CC0_REGNUM}, \
{(1 << CRIS_MOF_REGNUM) \
| (1 << CRIS_SRP_REGNUM)}, \
{CRIS_SPECIAL_REGS_CONTENTS}, \
- {CRIS_SPECIAL_REGS_CONTENTS \
- | (1 << CRIS_ACR_REGNUM)}, \
- {(0xffff | CRIS_FAKED_REGS_CONTENTS) \
- & ~(1 << CRIS_ACR_REGNUM)}, \
- {(0xffff | CRIS_FAKED_REGS_CONTENTS \
- | CRIS_SPECIAL_REGS_CONTENTS) \
- & ~(1 << CRIS_ACR_REGNUM)}, \
{0xffff | CRIS_FAKED_REGS_CONTENTS}, \
{0xffff | CRIS_FAKED_REGS_CONTENTS \
| CRIS_SPECIAL_REGS_CONTENTS} \
}
#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) == CRIS_ACR_REGNUM ? ACR_REGS : \
- (REGNO) == CRIS_MOF_REGNUM ? MOF_REGS : \
+ ((REGNO) == CRIS_MOF_REGNUM ? MOF_REGS : \
(REGNO) == CRIS_SRP_REGNUM ? SRP_REGS : \
(REGNO) == CRIS_CC0_REGNUM ? CC0_REGS : \
GENERAL_REGS)
#define BASE_REG_CLASS GENERAL_REGS
-#define MODE_CODE_BASE_REG_CLASS(MODE, AS, OCODE, ICODE) \
- ((OCODE) != POST_INC ? BASE_REG_CLASS : GENNONACR_REGS)
-
#define INDEX_REG_CLASS GENERAL_REGS
/* Since it uses reg_renumber, it is safe only once reg_renumber
@@ -60,7 +60,6 @@ (define_constants
[(CRIS_STATIC_CHAIN_REGNUM 7)
(CRIS_REAL_FP_REGNUM 8)
(CRIS_SP_REGNUM 14)
- (CRIS_ACR_REGNUM 15)
(CRIS_SRP_REGNUM 16)
(CRIS_MOF_REGNUM 17)
(CRIS_AP_REGNUM 18)