From patchwork Wed Feb 2 00:22:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 50661 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BB5B93857C47 for ; Wed, 2 Feb 2022 00:23:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BB5B93857C47 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1643761404; bh=koNAHmQB2g4BkN0ra7LJ5CrD5xcf1GZBgVmM8r4wkIA=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=bREnxmtR8ujfXIvByVlXhDo9Zy6t2GcLtuzehJ1jS/yElZy+L9P/i+lnDfnMZNT9w t86hgYWVkI57VSNuQX9nRSwQDUTPRem9RJePtMkoe/qOuXwdxESJJre2ktQkMgnLFU 9YNxWd3wKW3Is017Wkk3kocWVylhbLHJoYyIEC1w= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by sourceware.org (Postfix) with ESMTPS id 853DB385BF86 for ; Wed, 2 Feb 2022 00:22:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 853DB385BF86 To: Subject: [PATCH 1/5] cris: Don't default to -mmul-bug-workaround MIME-Version: 1.0 Message-ID: <20220202002221.218BE20438@pchp3.se.axis.com> Date: Wed, 2 Feb 2022 01:22:21 +0100 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hans-Peter Nilsson via Gcc-patches From: Hans-Peter Nilsson Reply-To: Hans-Peter Nilsson Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This flips the default for the errata handling for an old version (TL;DR: workaround: no multiply instruction last on a cache-line). Newer versions of the CRIS cpu don't have that bug. While the impact of the workaround is very marginal (coremark: less than .05% larger, less than .0005% slower) it's an irritating pseudorandom factor when assessing the impact of other changes. Also, fix a wart requiring changes to more than TARGET_DEFAULT to flip the default. People building old kernels or operating systems to run on ETRAX 100 LX are advised to pass "-mmul-bug-workaround". gcc: * config/cris/cris.h (TARGET_DEFAULT): Don't include MASK_MUL_BUG. (MUL_BUG_ASM_DEFAULT): New macro. (MAYBE_AS_NO_MUL_BUG_ABORT): Define in terms of MUL_BUG_ASM_DEFAULT. * doc/invoke.texi (CRIS Options, -mmul-bug-workaround): Adjust accordingly. --- gcc/config/cris/cris.h | 19 ++++++++++++++++--- gcc/doc/invoke.texi | 2 +- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index b274e1166203..9245d7886929 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -153,7 +153,9 @@ extern int cris_cpu_version; #ifdef HAVE_AS_NO_MUL_BUG_ABORT_OPTION #define MAYBE_AS_NO_MUL_BUG_ABORT \ - "%{mno-mul-bug-workaround:-no-mul-bug-abort} " + "%{mno-mul-bug-workaround:-no-mul-bug-abort} " \ + "%{mmul-bug-workaround:-mul-bug-abort} " \ + "%{!mmul-bug-workaround:%{!mno-mul-bug-workaround:" MUL_BUG_ASM_DEFAULT "}} " #else #define MAYBE_AS_NO_MUL_BUG_ABORT #endif @@ -255,15 +257,26 @@ extern int cris_cpu_version; (MASK_SIDE_EFFECT_PREFIXES + MASK_STACK_ALIGN \ + MASK_CONST_ALIGN + MASK_DATA_ALIGN \ + MASK_ALIGN_BY_32 \ - + MASK_PROLOGUE_EPILOGUE + MASK_MUL_BUG) + + MASK_PROLOGUE_EPILOGUE) # else /* 0 */ # define TARGET_DEFAULT \ (MASK_SIDE_EFFECT_PREFIXES + MASK_STACK_ALIGN \ + MASK_CONST_ALIGN + MASK_DATA_ALIGN \ - + MASK_PROLOGUE_EPILOGUE + MASK_MUL_BUG) + + MASK_PROLOGUE_EPILOGUE) # endif #endif +/* Don't depend on the assembler default setting for the errata machinery; + always pass the option to turn it on or off explicitly. But, we have to + decide on which is the *GCC* default, and for that we should only need to + consider what's in TARGET_DEFAULT; no other changes should be necessary. */ + +#if (TARGET_DEFAULT & MASK_MUL_BUG) +#define MUL_BUG_ASM_DEFAULT "-mul-bug-abort" +#else +#define MUL_BUG_ASM_DEFAULT "-no-mul-bug-abort" +#endif + /* Local, providing a default for cris_cpu_version. */ #define CRIS_DEFAULT_CPU_VERSION TARGET_CPU_DEFAULT diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cfd415110cdf..7af5c51cc3c7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -22268,7 +22268,7 @@ The options @option{-metrax4} and @option{-metrax100} are synonyms for @opindex mmul-bug-workaround @opindex mno-mul-bug-workaround Work around a bug in the @code{muls} and @code{mulu} instructions for CPU -models where it applies. This option is active by default. +models where it applies. This option is disabled by default. @item -mpdebug @opindex mpdebug From patchwork Wed Feb 2 00:23:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 50662 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7B3C7385B80B for ; Wed, 2 Feb 2022 00:25:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7B3C7385B80B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1643761555; bh=t55VqTAYoArhtKpZLbQyK4mGJkvmm+ksKgGQ+gsEunY=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=Zg9gwvCCiSlFIykPQzWHBlpbkusnr1mATH/Cd89EqHFB33lMF5vMKXRRlz270KdQd eHF0TQ2A8wznANWfVu5a6JEs6MXXgSM+ZkY37ND8U4AbLo8MqK29ChBL4FlJIY99Wu azt7xyTcxeE1XSDUF0dVLSonFS67S/wz8qunpcUU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by sourceware.org (Postfix) with ESMTPS id 8E127385C418 for ; Wed, 2 Feb 2022 00:23:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8E127385C418 To: Subject: [PATCH 2/5] cris: For expanded movsi, don't match operands we know will be reloaded MIME-Version: 1.0 Message-ID: <20220202002313.5D2FC20439@pchp3.se.axis.com> Date: Wed, 2 Feb 2022 01:23:13 +0100 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hans-Peter Nilsson via Gcc-patches From: Hans-Peter Nilsson Reply-To: Hans-Peter Nilsson Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" In a session investigating unexpected fallout from a change, I noticed reload needs one operand being a register to make an informed decision. It can happen that there's just a constant and a memory operand, as in: (insn 668 667 42 104 (parallel [ (set (mem:SI (plus:SI (reg/v/f:SI 347 [ fs ]) (const_int 168 [0xa8])) \ [1 fs_126(D)->regs.cfa_how+0 S4 A8]) (const_int 2 [0x2])) (clobber (reg:CC 19 dccr)) ]) "<...>/gcc/libgcc/unwind-dw2.c":1121:21 22 {*movsi_internal} (expr_list:REG_UNUSED (reg:CC 19 dccr) (nil))) This was helpfully created by combine. When this happens, reload can't check for costs and preferred register classes, (both operands will start with NO_REGS as the preferred class) and will default to the constraints order in the insn in reload. (Which also does its own temporary merge in find_reloads, but that's a different story.) Better don't match the simple cases. Beware that subregs have to be matched. I'm doing this just for word_mode (SI) for now, but may repeat this for the other valid modes as well. In particular, that goes for DImode as I see the expanded movdi does *almost* this, but uses register_operand instead of REG_S_P (from cris.h). Using REG_S_P is the right choice here because register_operand also matches (subreg (mem ...) ...) *until* reload is done. By itself it's just a sub-0.1% performance win (coremark). Also removing a stale comment. gcc: * config/cris/cris.md ("*movsi_internal"): Conditionalize on (sub-)register operands or operand 1 being 0. --- gcc/config/cris/cris.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index bc8d7584f6d9..9d1c179d5211 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -583,9 +583,10 @@ (define_insn "*movsi_internal" (match_operand:SI 1 "general_operand" "r,Q>,M,M, I,r, M,n,g,r,x, rQ>,x,gi")) (clobber (reg:CC CRIS_CC0_REGNUM))] - ;; Note that we prefer not to use the S alternative (if for some reason - ;; it competes with others) above, but g matches S. - "" + ;; Avoid matching insns we know must be reloaded. Without one + ;; operand being a (pseudo-)register, reload chooses + ;; reload-registers suboptimally. + "REG_S_P (operands[0]) || REG_S_P (operands[1]) || operands[1] == const0_rtx" { /* Better to have c-switch here; it is worth it to optimize the size of move insns. The alternative would be to try to find more constraint From patchwork Wed Feb 2 00:24:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 50663 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C6ED3857C47 for ; Wed, 2 Feb 2022 00:26:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8C6ED3857C47 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1643761611; bh=QXVqjnO1a/rGl5+0Xed6ZgypfSiD83bZmdImUSnOZ4E=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=f1YKu3x0JzXahRAVvWvu37q9mmX+cobiGPlfoE0CKRLmUuhBljLbrJqOQmll+nft9 l1oeIWKiCbg0ZxHdTh4ehF/Vlf124urOiZpj0yOmsew+YBI3n6iMv9Sz+aZj9ncKvb xsluEzA+R28o7OsNE2sqcVMuGOMCTyn+C6c6plOw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by sourceware.org (Postfix) with ESMTPS id 972F23857C47 for ; Wed, 2 Feb 2022 00:24:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 972F23857C47 To: Subject: [PATCH 3/5] cris: Remove CRIS v32 ACR artefacts MIME-Version: 1.0 Message-ID: <20220202002401.4305620439@pchp3.se.axis.com> Date: Wed, 2 Feb 2022 01:24:01 +0100 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hans-Peter Nilsson via Gcc-patches From: Hans-Peter Nilsson Reply-To: Hans-Peter Nilsson Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This is the change to which I alluded to this in r11-220 / d0780379c1b6 as "causes extra register moves in libgcc". It has unfortunate side-effects due to the change in register-class topology. There's a slight improvement in coremark numbers (< 0.07%) though also increase in code size total (< 0.7%) but looking at the individual changes in functions, it's all-over (-7..+7%). Looking specifically at functions that improved in speed, it's also both plus and minus in code sizes. It's unworkable to separate improvements from regressions for this case. I'll follow up with patches to restore the previous code quality, in both size and speed. gcc: * config/cris/constraints.md (define_register_constraint "b"): Now GENERAL_REGS. * config/cris/cris.md (CRIS_ACR_REGNUM): Remove. * config/cris/cris.h: (reg_class, REG_CLASS_NAMES) (REG_CLASS_CONTENTS): Remove ACR_REGS, SPEC_ACR_REGS, GENNONACR_REGS, and SPEC_GENNONACR_REGS. * config/cris/cris.cc (cris_preferred_reload_class): Don't mention ACR_REGS and return GENERAL_REGS instead of GENNONACR_REGS. --- gcc/config/cris/constraints.md | 7 ++++++- gcc/config/cris/cris.cc | 5 ++--- gcc/config/cris/cris.h | 27 +++++---------------------- gcc/config/cris/cris.md | 1 - 4 files changed, 13 insertions(+), 27 deletions(-) diff --git a/gcc/config/cris/constraints.md b/gcc/config/cris/constraints.md index 01ec12c4cf2a..83fab622717d 100644 --- a/gcc/config/cris/constraints.md +++ b/gcc/config/cris/constraints.md @@ -18,7 +18,12 @@ ;; . ;; Register constraints. -(define_register_constraint "b" "GENNONACR_REGS" + +;; Kept for compatibility. It used to exclude the CRIS v32 +;; register "ACR", which was like GENERAL_REGS except it +;; couldn't be used for autoincrement, and intended mainly +;; for use in user asm statements. +(define_register_constraint "b" "GENERAL_REGS" "@internal") (define_register_constraint "h" "MOF_REGS" diff --git a/gcc/config/cris/cris.cc b/gcc/config/cris/cris.cc index a7807b3cc25c..264439c7654a 100644 --- a/gcc/config/cris/cris.cc +++ b/gcc/config/cris/cris.cc @@ -1663,13 +1663,12 @@ cris_reload_address_legitimized (rtx x, static reg_class_t cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) { - if (rclass != ACR_REGS - && rclass != MOF_REGS + if (rclass != MOF_REGS && rclass != MOF_SRP_REGS && rclass != SRP_REGS && rclass != CC0_REGS && rclass != SPECIAL_REGS) - return GENNONACR_REGS; + return GENERAL_REGS; return rclass; } diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 9245d7886929..6edfe13d92cc 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -436,19 +436,15 @@ extern int cris_cpu_version; /* Node: Register Classes */ -/* We need a separate register class to handle register allocation for - ACR, since it can't be used for post-increment. - - It's not obvious, but having subunions of all movable-between +/* It's not obvious, but having subunions of all movable-between register classes does really help register allocation (pre-IRA comment). */ enum reg_class { NO_REGS, - ACR_REGS, MOF_REGS, SRP_REGS, CC0_REGS, + MOF_REGS, SRP_REGS, CC0_REGS, MOF_SRP_REGS, SPECIAL_REGS, - SPEC_ACR_REGS, GENNONACR_REGS, - SPEC_GENNONACR_REGS, GENERAL_REGS, + GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; @@ -457,9 +453,8 @@ enum reg_class #define REG_CLASS_NAMES \ {"NO_REGS", \ - "ACR_REGS", "MOF_REGS", "SRP_REGS", "CC0_REGS", \ + "MOF_REGS", "SRP_REGS", "CC0_REGS", \ "MOF_SRP_REGS", "SPECIAL_REGS", \ - "SPEC_ACR_REGS", "GENNONACR_REGS", "SPEC_GENNONACR_REGS", \ "GENERAL_REGS", "ALL_REGS"} #define CRIS_SPECIAL_REGS_CONTENTS \ @@ -472,37 +467,25 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ {0}, \ - {1 << CRIS_ACR_REGNUM}, \ {1 << CRIS_MOF_REGNUM}, \ {1 << CRIS_SRP_REGNUM}, \ {1 << CRIS_CC0_REGNUM}, \ {(1 << CRIS_MOF_REGNUM) \ | (1 << CRIS_SRP_REGNUM)}, \ {CRIS_SPECIAL_REGS_CONTENTS}, \ - {CRIS_SPECIAL_REGS_CONTENTS \ - | (1 << CRIS_ACR_REGNUM)}, \ - {(0xffff | CRIS_FAKED_REGS_CONTENTS) \ - & ~(1 << CRIS_ACR_REGNUM)}, \ - {(0xffff | CRIS_FAKED_REGS_CONTENTS \ - | CRIS_SPECIAL_REGS_CONTENTS) \ - & ~(1 << CRIS_ACR_REGNUM)}, \ {0xffff | CRIS_FAKED_REGS_CONTENTS}, \ {0xffff | CRIS_FAKED_REGS_CONTENTS \ | CRIS_SPECIAL_REGS_CONTENTS} \ } #define REGNO_REG_CLASS(REGNO) \ - ((REGNO) == CRIS_ACR_REGNUM ? ACR_REGS : \ - (REGNO) == CRIS_MOF_REGNUM ? MOF_REGS : \ + ((REGNO) == CRIS_MOF_REGNUM ? MOF_REGS : \ (REGNO) == CRIS_SRP_REGNUM ? SRP_REGS : \ (REGNO) == CRIS_CC0_REGNUM ? CC0_REGS : \ GENERAL_REGS) #define BASE_REG_CLASS GENERAL_REGS -#define MODE_CODE_BASE_REG_CLASS(MODE, AS, OCODE, ICODE) \ - ((OCODE) != POST_INC ? BASE_REG_CLASS : GENNONACR_REGS) - #define INDEX_REG_CLASS GENERAL_REGS /* Since it uses reg_renumber, it is safe only once reg_renumber diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index 9d1c179d5211..9d9eb8b7dbbf 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -60,7 +60,6 @@ (define_constants [(CRIS_STATIC_CHAIN_REGNUM 7) (CRIS_REAL_FP_REGNUM 8) (CRIS_SP_REGNUM 14) - (CRIS_ACR_REGNUM 15) (CRIS_SRP_REGNUM 16) (CRIS_MOF_REGNUM 17) (CRIS_AP_REGNUM 18) From patchwork Wed Feb 2 00:24:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 50664 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AE87C385AC09 for ; Wed, 2 Feb 2022 00:28:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AE87C385AC09 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1643761696; bh=ZB+4buYrOvmhddk8S1uXvz+NaqvuvDg3RUb/i9bWcxQ=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=QWu0PqCVjuRCsbE/Gugq35578De6fNSbLcmQ1kVuZM0fgplFPwZXrhRwfRbSLrKtO 6vg3msJFBB29iqsQeRrw0vVjg6SY9GEZ0JiA+aFIc5tv2mudiDrihnKwzeayQ7sOjz AgmduDY7iu85VdfIbXO21QY/qQ3iyRPeWm5gkwBc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by sourceware.org (Postfix) with ESMTPS id 9B3D1385781E for ; Wed, 2 Feb 2022 00:24:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9B3D1385781E To: Subject: [PATCH 4/5] cris: Don't discriminate against ALL_REGS in TARGET_REGISTER_MOVE_COST MIME-Version: 1.0 Message-ID: <20220202002455.43B5620439@pchp3.se.axis.com> Date: Wed, 2 Feb 2022 01:24:55 +0100 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hans-Peter Nilsson via Gcc-patches From: Hans-Peter Nilsson Reply-To: Hans-Peter Nilsson Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" When the tightest class including both SPECIAL_REGS and GENERAL_REGS is ALL_REGS, artificially special-casing for *either* to or from, hits artificially hard. This gets the port back to the code quality before the previous patch ("cris: Remove CRIS v32 ACR artefacts") - except for_vfprintf_r and _vfiprintf_r in newlib (still .8 and .4% larger). gcc: * config/cris/cris.cc (cris_register_move_cost): Remove special pre-ira extra cost for ALL_REGS. --- gcc/config/cris/cris.cc | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/gcc/config/cris/cris.cc b/gcc/config/cris/cris.cc index 264439c7654a..4f977221f459 100644 --- a/gcc/config/cris/cris.cc +++ b/gcc/config/cris/cris.cc @@ -1683,20 +1683,10 @@ cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, their move cost within that class is higher. How about 7? That's 3 for a move to a GENERAL_REGS register, 3 for the move from the GENERAL_REGS register, and 1 for the increased register pressure. - Also, it's higher than the memory move cost, as it should. - We also do this for ALL_REGS, since we don't want that class to be - preferred (even to memory) at all where GENERAL_REGS doesn't fit. - Whenever it's about to be used, it's for SPECIAL_REGS. If we don't - present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be - used when a GENERAL_REGS should be used, even if there are call-saved - GENERAL_REGS left to allocate. This is because the fall-back when - the most preferred register class isn't available, isn't the next - (or next good) wider register class, but the *most widest* register - class. FIXME: pre-IRA comment, perhaps obsolete now. */ - - if ((reg_classes_intersect_p (from, SPECIAL_REGS) - && reg_classes_intersect_p (to, SPECIAL_REGS)) - || from == ALL_REGS || to == ALL_REGS) + Also, it's higher than the memory move cost, as it should be. */ + + if (reg_classes_intersect_p (from, SPECIAL_REGS) + && reg_classes_intersect_p (to, SPECIAL_REGS)) return 7; /* Make moves to/from SPECIAL_REGS slightly more expensive, as we From patchwork Wed Feb 2 00:25:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 50665 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C2B243857C45 for ; Wed, 2 Feb 2022 00:29:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C2B243857C45 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1643761752; bh=d8PwuGRr8gELFeZCshi0MnC7BBw/YMi1223raTrOm38=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=IXH/IkqEktJdvkaBbGlI4GCQD6R1ajJuHJxo/1ERytESI5mHgEVR9yVg1n2SPwZGL 0cImJmCMZYCGwvWKvFmSRA4GqAQ2IsOj4OvQ05dOxw5uDykUIeKYutiBek/ZNw75Ri 88JNMLoBUdMTuq+flxdR7V6dNAJKmraOB/E0f6UY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by sourceware.org (Postfix) with ESMTPS id 6759C385C403 for ; Wed, 2 Feb 2022 00:25:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6759C385C403 To: Subject: [PATCH 5/5] cris: Reload using special-regs before general-regs MIME-Version: 1.0 Message-ID: <20220202002531.12CFA20439@pchp3.se.axis.com> Date: Wed, 2 Feb 2022 01:25:31 +0100 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hans-Peter Nilsson via Gcc-patches From: Hans-Peter Nilsson Reply-To: Hans-Peter Nilsson Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" On code where reload has an effect (i.e. quite rarely, just enough to be noticeable), this change gets code quality back to the situation prior to "Remove CRIS v32 ACR artefacts". We had from IRA a pseudoregister marked to be reloaded from a union of all allocatable registers (here: SPEC_GENNONACR_REGS) but where the register-class corresponding to the constraint for the register-type alternative (here: GENERAL_REGS) was *not* a subset of that class: SPEC_GENNONACR_REGS (and GENNONACR_REGS) had a one-register "hole" for the ACR register, a register present in GENERAL_REGS. Code in reload.cc:find_reloads adds 4 to the cost of a register-type alternative that is neither a subset of the preferred register class nor vice versa and thus reload thinks it can't use. It would be preferable to look for a non-empty intersection of the two, and use that intersection for that alternative, something that can't be expressed because a register class can't be formed from a random register set. The effect was here that the GENERAL_REGS to/from memory alternatives ("r") had their cost raised such that the SPECIAL_REGS alternatives ("x") looked better. This happened to improve code quality just a little bit compared to GENERAL_REGS being chosen. Anyway, with the improved CRIS register-class topology, the subset-checking code no longer has the GENERAL_REGS-demoting effect. To get the same quality, we have to adjust the port such that SPECIAL_REGS are specifically preferred when possible and advisible, i.e. when there's at least two of those registers as for the CPU variant with multiplication (which happens to be the variant maintained for performance). For the move-pattern, the obvious method may seem to simply "curse" the constraints of some alternatives (by prepending one of the "?!^$" characters) but that method can't be used, because we want the effect to be conditional on the CPU variant. It'd also be a shame to split the "*movsi_internal" into two CPU-variants (with different cursing). Iterators would help, but it still seems unwieldy. Instead, add copies of the GENERAL_REGS variants (to the SPECIAL_REGS alternatives) on the "other" side, and make use of the "enabled" attribute to activate just the desired order of alternatives. gcc: * config/cris/cris.cc (cris_preferred_reload_class): Reject "eliminated" registers and small-enough constants unless reloaded into a class that is a subset of GENERAL_REGS. * config/cris/cris.md (attribute "cpu_variant"): New. (attribute "enabled"): Conditionalize on a matching attribute cpu_variant, if specified. ("*movsi_internal"): For moves to and from memory, add cpu-variant-enabled variants for "r" alternatives on the far side of the "x" alternatives, preferring the "x" ones only for variants where MOF is present (in addition to SRP). --- gcc/config/cris/cris.cc | 13 ++++++++++++- gcc/config/cris/cris.md | 25 ++++++++++++++++++++----- 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/gcc/config/cris/cris.cc b/gcc/config/cris/cris.cc index 4f977221f459..f0017d630229 100644 --- a/gcc/config/cris/cris.cc +++ b/gcc/config/cris/cris.cc @@ -1661,7 +1661,7 @@ cris_reload_address_legitimized (rtx x, a bug. */ static reg_class_t -cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) +cris_preferred_reload_class (rtx x, reg_class_t rclass) { if (rclass != MOF_REGS && rclass != MOF_SRP_REGS @@ -1670,6 +1670,17 @@ cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) && rclass != SPECIAL_REGS) return GENERAL_REGS; + /* We can't make use of something that's not a general register when + reloading an "eliminated" register (i.e. something that has turned into + e.g. sp + const_int). */ + if (GET_CODE (x) == PLUS && !reg_class_subset_p (rclass, GENERAL_REGS)) + return NO_REGS; + + /* Avoid putting constants into a special register, where the instruction is + shorter if loaded into a general register. */ + if (satisfies_constraint_P (x) && !reg_class_subset_p (rclass, GENERAL_REGS)) + return NO_REGS; + return rclass; } diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index 9d9eb8b7dbbf..dd7094163784 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -153,9 +153,20 @@ (define_delay (eq_attr "slottable" "has_return_slot") (not (match_test "dead_or_set_regno_p (insn, CRIS_SRP_REGNUM)"))) (nil) (nil)]) +;; Enable choosing particular instructions. The discriminator choice +;; "v0" stands for "pre-v10", for brevity. +(define_attr "cpu_variant" "default,v0,v10" (const_string "default")) + (define_attr "enabled" "no,yes" (if_then_else - (eq_attr "cc_enabled" "normal") + (and + (eq_attr "cc_enabled" "normal") + (ior + (eq_attr "cpu_variant" "default") + (and (eq_attr "cpu_variant" "v10") + (match_test "TARGET_HAS_MUL_INSNS")) + (and (eq_attr "cpu_variant" "v0") + (not (match_test "TARGET_HAS_MUL_INSNS"))))) (const_string "yes") (const_string "no"))) @@ -578,9 +589,9 @@ (define_expand "movsi" (define_insn "*movsi_internal" [(set (match_operand:SI 0 "nonimmediate_operand" - "=r,r, r,Q>,r,Q>,g,r,r,g,rQ>,x, m,x") + "=r,r, r,Q>,r,Q>,g,r,r,g,rQ>,x, m,x, Q>,r,g") (match_operand:SI 1 "general_operand" - "r,Q>,M,M, I,r, M,n,g,r,x, rQ>,x,gi")) + "r,Q>,M,M, I,r, M,n,g,r,x, rQ>,x,gi,r, g,r")) (clobber (reg:CC CRIS_CC0_REGNUM))] ;; Avoid matching insns we know must be reloaded. Without one ;; operand being a (pseudo-)register, reload chooses @@ -597,6 +608,9 @@ (define_insn "*movsi_internal" case 5: case 8: case 9: + case 14: + case 15: + case 16: return "move.d %1,%0"; case 10: @@ -634,9 +648,10 @@ (define_insn "*movsi_internal" gcc_unreachable (); } } - [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,yes,yes,no,no") + [(set_attr "cpu_variant" "*,*,*,*,*,v0,*,*,v0,v0,*,*,*,*,v10,v10,v10") + (set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,yes,yes,no,no,yes,no,no") (set_attr "cc" - "*,*,none,none,*,none,none,*,*,none,none,none,none,none")]) + "*,*,none,none,*,none,none,*,*,none,none,none,none,none,none,*,none")]) ;; FIXME: See movsi.