Show patches with: Search = RISC-V       |    Archived = No       |   3475 patches
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Patch Series rb/tb S/W/F Date Submitter Delegate State
[v3,2/4] RISC-V: Add Zicfilp ISA extension. [v3,1/4] RISC-V: Add Zicfiss ISA extension. - - 51- 2025-01-15 Monk Chiang Dropped
[v3,1/4] RISC-V: Add Zicfiss ISA extension. [v3,1/4] RISC-V: Add Zicfiss ISA extension. - - 51- 2025-01-15 Monk Chiang Dropped
[committed,RISC-V,PR,target/118170] Add HF div/sqrt reservation [committed,RISC-V,PR,target/118170] Add HF div/sqrt reservation - - 6-2 2025-01-15 Jeff Law Committed
[v2] RISC-V: Fix vsetvl compatibility predicate [PR118154]. [v2] RISC-V: Fix vsetvl compatibility predicate [PR118154]. - - 9-1 2025-01-14 Robin Dapp Committed
RISC-V: Disable RV64-only crc testcases for RV32 RISC-V: Disable RV64-only crc testcases for RV32 - - 10-- 2025-01-14 Bohan Lei JeffreyALaw Committed
[COMMITTED] RISC-V: fix thinko in riscv_register_move_cost () [COMMITTED] RISC-V: fix thinko in riscv_register_move_cost () - - 6-2 2025-01-13 Vineet Gupta Committed
RISC-V: Fix the result error caused by not updating ratio when using "use_max_sew" to merge vsetvl. RISC-V: Fix the result error caused by not updating ratio when using "use_max_sew" to merge vsetvl. - - 9-1 2025-01-13 Jin Ma Committed
RISC-V: Fix program logic errors caused by data truncation on 32-bit host for zbs, such as i386. RISC-V: Fix program logic errors caused by data truncation on 32-bit host for zbs, such as i386. - - 9-1 2025-01-13 Jin Ma JeffreyALaw Committed
[v2,4/4] RISC-V: Add -fcf-protection=[full|branch|return] to enable zicfiss, zicfilp. [v2,1/4] RISC-V: Add Zicfiss ISA extension. - - 811 2025-01-13 Monk Chiang kitoc Dropped
[v2,3/4] RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extension [v2,1/4] RISC-V: Add Zicfiss ISA extension. - - 91- 2025-01-13 Monk Chiang kitoc Dropped
[v2,2/4] RISC-V: Add Zicfilp ISA extension. [v2,1/4] RISC-V: Add Zicfiss ISA extension. - - 91- 2025-01-13 Monk Chiang kitoc Dropped
[v2,1/4] RISC-V: Add Zicfiss ISA extension. [v2,1/4] RISC-V: Add Zicfiss ISA extension. - - 91- 2025-01-13 Monk Chiang kitoc Dropped
[2/2] RISC-V: Remove zba check in bitwise and ashift reassociation [PR 115921] RISC-V bitwise-ashift reassoc improvements [PR 115921] - - 10-- 2025-01-12 Xi Ruoyao JeffreyALaw Committed
[1/2] RISC-V: Improve bitwise and ashift reassociation for single-bit immediate without zbs [PR 115… RISC-V bitwise-ashift reassoc improvements [PR 115921] - - 10-- 2025-01-12 Xi Ruoyao JeffreyALaw Committed
RISC-V: fix thinko in riscv_register_move_cost () RISC-V: fix thinko in riscv_register_move_cost () - - 10-- 2025-01-11 Vineet Gupta JeffreyALaw Committed
RISC-V: Fix riscv_modes_tieable_p RISC-V: Fix riscv_modes_tieable_p - - -13 2025-01-10 Zhijin Zeng Deferred
RISC-V: Let strided loads/stores demand proper SEW/LMUL [PR118154]. RISC-V: Let strided loads/stores demand proper SEW/LMUL [PR118154]. - - 6-- 2025-01-10 Robin Dapp Superseded
Subject: [PATCH] RISC-V: testsuite: Skip test with -flto. Subject: [PATCH] RISC-V: testsuite: Skip test with -flto. - - 6-- 2025-01-10 Robin Dapp JeffreyALaw Committed
RISC-V: testsuite: fix target selector for sync_char_short RISC-V: testsuite: fix target selector for sync_char_short - - 6-2 2025-01-09 Edwin Lu Committed
回复: Re: [PATCH] RISC-V: Refine registered_functions list for rvv overloaded intrinsics. 回复: Re: [PATCH] RISC-V: Refine registered_functions list for rvv overloaded intrinsics. - - -21 2025-01-09 xuli1@eswincomputing.com JuzheZhong Committed
RISC-V: Refine registered_functions list for rvv overloaded intrinsics. RISC-V: Refine registered_functions list for rvv overloaded intrinsics. - - 7-- 2025-01-08 xuli1@eswincomputing.com JuzheZhong Committed
[V4,2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - -12 2025-01-08 yulong kitoc Deferred
[V4,1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - -11 2025-01-08 yulong kitoc Deferred
[COMMITTED] RISC-V: vector absolute difference expander [PR117722] [COMMITTED] RISC-V: vector absolute difference expander [PR117722] - - 6-2 2025-01-07 Vineet Gupta Committed
testsuite: enable effective-target sync_char_short on RISC-V testsuite: enable effective-target sync_char_short on RISC-V - - 7-3 2025-01-07 Andreas Schwab JeffreyALaw Committed
[v4] RISC-V: Fix code gen for reduction with length 0 [PR118182] [v4] RISC-V: Fix code gen for reduction with length 0 [PR118182] - - 91- 2025-01-06 Kito Cheng Committed
[v2,4/4] testsuite: RISC-V: Skip tests providing -march for ILP32E/ILP64E ABIs testsuite: RISC-V: Improve support for RV32E - - 6-- 2025-01-04 Dimitar Dimitrov JeffreyALaw Committed
[v2,3/4] testsuite: RISC-V: Skip tests using -mcpu= for ILP32E/ILP64E ABIs testsuite: RISC-V: Improve support for RV32E - - 6-- 2025-01-04 Dimitar Dimitrov JeffreyALaw Committed
[v2,2/4] testsuite: RISC-V: Skip V and Zvbb tests for ILP32E/ILP64E ABIs testsuite: RISC-V: Improve support for RV32E - - 6-- 2025-01-04 Dimitar Dimitrov JeffreyALaw Committed
[v2,1/4] testsuite: RISC-V: Add effective target for E ABI variant testsuite: RISC-V: Improve support for RV32E - - 6-- 2025-01-04 Dimitar Dimitrov JeffreyALaw Committed
[2/2] RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1. [1/2] Match:Support IMM=-1 for signed scalar SAT_ADD IMM form1 - - -11 2025-01-02 xuli1@eswincomputing.com Deferred
[2/2] RISC-V: Add testcases for signed vector SAT_ADD IMM form 1 [1/2] Match:Support signed vector SAT_ADD IMM form 1 - - -11 2025-01-02 xuli1@eswincomputing.com Deferred
RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4 RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4 - - 6-- 2025-01-02 xuli1@eswincomputing.com Committed
[committed,RISC-V,PR,target/115375] Fix expected dump output [committed,RISC-V,PR,target/115375] Fix expected dump output - - 6-- 2024-12-31 Jeff Law Committed
[to-be-committed,RISC-V,PR,target/106544] Avoid ICEs due to bogus asms [to-be-committed,RISC-V,PR,target/106544] Avoid ICEs due to bogus asms - - 51- 2024-12-30 Jeff Law Committed
[to-be-committed,RISC-V,PR,target/118122] Fix modes in recently added risc-v pattern [to-be-committed,RISC-V,PR,target/118122] Fix modes in recently added risc-v pattern - - 51- 2024-12-30 Jeff Law Committed
[to-be-committed,RISC-V,V2,PR,target/116715] Remove bogus bitmanip pattern [to-be-committed,RISC-V,V2,PR,target/116715] Remove bogus bitmanip pattern - - 6-- 2024-12-29 Jeff Law Committed
[to-be-committed,RISC-V,PR,target/116686] Remove bogus bitmanip pattern [to-be-committed,RISC-V,PR,target/116686] Remove bogus bitmanip pattern - - 5-1 2024-12-29 Jeff Law Superseded
[V3,2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - -11 2024-12-25 yulong kitoc Superseded
[V3,1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - -11 2024-12-25 yulong kitoc Superseded
[pushed] wwwdocs: readings: Update RISC-V specifications link [pushed] wwwdocs: readings: Update RISC-V specifications link - - -11 2024-12-25 Gerald Pfeifer Committed
[v3] RISC-V: Fix code gen for reduction with length 0 [PR118182] [v3] RISC-V: Fix code gen for reduction with length 0 [PR118182] - - 411 2024-12-23 Kito Cheng Superseded
[v2] RISC-V: Fix code gen for reduction with length 0 [PR118182] [v2] RISC-V: Fix code gen for reduction with length 0 [PR118182] - - -11 2024-12-23 Kito Cheng Dropped
RISC-V: Fix code gen for reduction with length 0 [PR118182] RISC-V: Fix code gen for reduction with length 0 [PR118182] - - -11 2024-12-23 Kito Cheng Dropped
RISC-V: Move fortran testcase to gfortran.target RISC-V: Move fortran testcase to gfortran.target - - 6-- 2024-12-23 Kito Cheng Committed
[RFC,v2] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand [RFC,v2] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand - - 6-- 2024-12-23 yunzezhu@linux.alibaba.com JeffreyALaw Rejected
[V2,2/2] RISC-V: Add intrinsic testcases for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - -11 2024-12-23 yulong Superseded
[V2,1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - -11 2024-12-23 yulong Superseded
[v2] RISC-V: vector absolute difference expander [PR117722] [v2] RISC-V: vector absolute difference expander [PR117722] - - 9-1 2024-12-20 Vineet Gupta JuzheZhong Committed
RISC-V: vector absolute difference expander [PR117722] RISC-V: vector absolute difference expander [PR117722] - - 9-1 2024-12-20 Vineet Gupta Superseded
[v1] RISC-V: Fix the the operand alignment for strided load/store pattern [NFC] [v1] RISC-V: Fix the the operand alignment for strided load/store pattern [NFC] - - 10-- 2024-12-20 Li, Pan2 Committed
[v1] RISC-V: Refine strided load/store testcase dump check to tree optimized [v1] RISC-V: Refine strided load/store testcase dump check to tree optimized - - 8-2 2024-12-20 Li, Pan2 Committed
RISC-V: List valid -mtune options only once RISC-V: List valid -mtune options only once - - 10-- 2024-12-19 Christoph Müllner kitoc Committed
[2/2] RISC-V: Add intrinsic testcases for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - -13 2024-12-19 yulong Superseded
[1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - -13 2024-12-19 yulong Superseded
RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand - - 91- 2024-12-19 yunzezhu@linux.alibaba.com Superseded
[v1,2/2] RISC-V: Adjust the strided store testcases check times on options [v1,1/2] RISC-V: Make vector strided store alias all other memories - - 811 2024-12-19 Li, Pan2 Committed
[v1,1/2] RISC-V: Make vector strided store alias all other memories [v1,1/2] RISC-V: Make vector strided store alias all other memories - - 413 2024-12-19 Li, Pan2 Committed
[RISC-V,PR,middle-end/118084] Fix brev based reflection code [RISC-V,PR,middle-end/118084] Fix brev based reflection code - - 11-1 2024-12-18 Jeff Law Committed
RISC-V: Expand shift count in Xmode in interleave pattern. RISC-V: Expand shift count in Xmode in interleave pattern. - - 12-- 2024-12-18 Robin Dapp Committed
Add RISC-V/rv64gc as a secondary platform Add RISC-V/rv64gc as a secondary platform - - 1-3 2024-12-18 Palmer Dabbelt JeffreyALaw Deferred
RISC-V: Disallow negative step for interleaving [PR117682]. RISC-V: Disallow negative step for interleaving [PR117682]. - - 10-2 2024-12-17 Robin Dapp Committed
RISC-V: Remove svvptc from riscv-ext-bitmask.def RISC-V: Remove svvptc from riscv-ext-bitmask.def 1 - 12-- 2024-12-16 Yangyu Chen Committed
RISC-V: optimization on checking certain bits set ((x & mask) == val) RISC-V: optimization on checking certain bits set ((x & mask) == val) - - 12-- 2024-12-16 Oliver Kozul JeffreyALaw Committed
RISC-V: Support for zilsd and zclsd extensions. RISC-V: Support for zilsd and zclsd extensions. - - 1011 2024-12-16 chendongyan Deferred
[v2,2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture [v2,1/2] RISC-V: Document thead-c906, xiangshan-nanhu, and generic-ooo - - 12-- 2024-12-15 Anton Blanchard JeffreyALaw Committed
[v2,1/2] RISC-V: Document thead-c906, xiangshan-nanhu, and generic-ooo [v2,1/2] RISC-V: Document thead-c906, xiangshan-nanhu, and generic-ooo - - 12-- 2024-12-15 Anton Blanchard JeffreyALaw Committed
RISC-V: Add Tenstorrent Ascalon 8 wide architecture RISC-V: Add Tenstorrent Ascalon 8 wide architecture - - 111- 2024-12-14 Anton Blanchard JeffreyALaw Superseded
[v2] RISC-V: Increase cost for vec_construct [PR118019]. [v2] RISC-V: Increase cost for vec_construct [PR118019]. - - 11-1 2024-12-13 Robin Dapp Committed
RISC-V: optimization by converting to LUI operands with LUI_AFTER_COMMON_LEADING_SHIFT RISC-V: optimization by converting to LUI operands with LUI_AFTER_COMMON_LEADING_SHIFT - - 11-1 2024-12-13 Oliver Kozul Rejected
[v3,2/2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases [v3,1/2] RISC-V: Update Xsfvfnrclip implementation. - - 111- 2024-12-13 Jiawei kitoc Committed
[v3,1/2] RISC-V: Update Xsfvfnrclip implementation. [v3,1/2] RISC-V: Update Xsfvfnrclip implementation. - - 101- 2024-12-13 Jiawei kitoc Committed
[2/2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases [1/2] RISC-V: Update Xsfvfnrclip implementation. - - 111- 2024-12-13 Jiawei Superseded
[1/2] RISC-V: Update Xsfvfnrclip implementation. [1/2] RISC-V: Update Xsfvfnrclip implementation. - - 101- 2024-12-13 Jiawei Superseded
回复：[PATCH] RISC-V: Increase cost for vec_construct [PR118019]. 回复：[PATCH] RISC-V: Increase cost for vec_construct [PR118019]. - - -13 2024-12-13 钟居哲 Superseded
RISC-V: Increase cost for vec_construct [PR118019]. RISC-V: Increase cost for vec_construct [PR118019]. - - 11-1 2024-12-13 Robin Dapp Superseded
[v1] RISC-V: Make vector strided load alias all other memories [v1] RISC-V: Make vector strided load alias all other memories - - 12-- 2024-12-13 Li, Pan2 Committed
[v2,5/5] RISC-V: Add new constraint R for register even-odd pairs New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 1011 2024-12-12 Kito Cheng JeffreyALaw Committed
[v2,4/5] RISC-V: Implment N modifier for printing the register number rather than the register name New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 1011 2024-12-12 Kito Cheng JeffreyALaw Committed
[v2,3/5] RISC-V: Rename internal operand modifier N to n New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 1011 2024-12-12 Kito Cheng JeffreyALaw Committed
[v2,2/5] RISC-V: Add cr and cf constraint New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 8-2 2024-12-12 Kito Cheng JeffreyALaw Committed
[v2,1/5] RISC-V: Rename constraint c0* to k0* New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 7-1 2024-12-12 Kito Cheng JeffreyALaw Committed
RISC-V: Emit vector shift pattern for const_vector [PR117353]. RISC-V: Emit vector shift pattern for const_vector [PR117353]. - - 11-1 2024-12-12 Robin Dapp Committed
RISC-V: Fix compress shuffle pattern [PR117383]. RISC-V: Fix compress shuffle pattern [PR117383]. - - 11-1 2024-12-11 Robin Dapp JeffreyALaw Committed
RISC-V: optimization by converting LUI operands with SMALL_AFTER_COMMON_TRAILING_SHIFT RISC-V: optimization by converting LUI operands with SMALL_AFTER_COMMON_TRAILING_SHIFT - - 11-1 2024-12-11 Oliver Kozul JeffreyALaw Deferred
[V2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip extension's testcases. [V2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip extension's testcases. - - 1011 2024-12-10 Liao Shihua JeffreyALaw Superseded
[3/3] testsuite: RISC-V: Explicitly specify ABI when passing -march testsuite: RISC-V: Improve support for RV32E - - 7-1 2024-12-09 Dimitar Dimitrov JeffreyALaw Superseded
[2/3] testsuite: RISC-V: Explicitly specify ABI when passing -mcpu= testsuite: RISC-V: Improve support for RV32E - - 7-1 2024-12-09 Dimitar Dimitrov JeffreyALaw Superseded
[1/3] testsuite: RISC-V: Explicitly specify ABI when adding V and Zvbb options testsuite: RISC-V: Improve support for RV32E - - 7-1 2024-12-09 Dimitar Dimitrov JeffreyALaw Superseded
[committed] RISC-V testsuite changes to test clmul expansion of CRCs [committed] RISC-V testsuite changes to test clmul expansion of CRCs - - 7-1 2024-12-09 Jeff Law Committed
RISC-V: Update Xsfvqmacc and Xsfvfnrclip extensions' testcases RISC-V: Update Xsfvqmacc and Xsfvfnrclip extensions' testcases - - 7-1 2024-12-09 Liao Shihua Superseded
[5/5] RISC-V: Add new constraint R for register even-odd pairs New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 611 2024-12-09 Kito Cheng Dropped
[4/5] RISC-V: Implment N modifier for printing the register number rather than the register name New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 611 2024-12-09 Kito Cheng Dropped
[3/5] RISC-V Rename internal operand modifier N to n New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 611 2024-12-09 Kito Cheng Dropped
[2/5] RISC-V: Add cr and cf constraint New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 7-1 2024-12-09 Kito Cheng Dropped
[1/5] RISC-V: Rename constraint c0* to k0* New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - 7-1 2024-12-09 Kito Cheng Dropped
[v1] RISC-V: Fix incorrect optimization options passing to partial [v1] RISC-V: Fix incorrect optimization options passing to partial - - 7-2 2024-12-09 Li, Pan2 Committed
[v1,6/6] RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - 12-- 2024-12-08 Li, Pan2 Committed
[v1,5/6] RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - 12-- 2024-12-08 Li, Pan2 Committed
[v1,4/6] RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - 12-- 2024-12-08 Li, Pan2 Committed
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