[v2,0/3] RISC-V: Support ZC* extensions.

  RISC-V Code Size Reduction(ZC*) extensions is a group of extensions 
which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]

The implementation of the RISC-V Code Size Reduction extension in GCC is
an important step towards making the RISC-V architecture more efficient.

The cooperation with OpenHW group has played a crucial role in this effort,
with facilitating the implementation, testing and validation. Currently
works can also find in OpenHW group's github repo.[2]

Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the 
specification, and Jeremy Bennett's patient guidance throughout the whole 
development process.a

V2 changes:
Fix Kito's comments in first version, Eswin assisted in optimizing the implementation of Zcmp extension:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617440.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617442.html

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620869.html


[1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification

[2] github.com/openhwgroup/corev-gcc

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by:	Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

  RISC-V: Minimal support for ZC extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for march args being passed.


Jiawei (3):
  RISC-V: Minimal support for ZC* extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for failed march args being passed.

 gcc/common/config/riscv/riscv-common.cc   | 38 +++++++++++++++++++++++
 gcc/config/riscv/riscv-c.cc               |  2 +-
 gcc/config/riscv/riscv-opts.h             | 16 ++++++++++
 gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +-
 gcc/config/riscv/riscv.cc                 | 11 ++++---
 gcc/config/riscv/riscv.h                  |  2 +-
 gcc/config/riscv/riscv.opt                |  3 ++
 gcc/testsuite/gcc.target/riscv/arch-22.c  |  5 +++
 gcc/testsuite/gcc.target/riscv/arch-23.c  |  5 +++
 9 files changed, 78 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c
  

Thanks Jiawei, v2 patch set are LGTM, but I would like to defer this until
binutils part has merged, I know you guys already implement that for a
while, so I think it’s almost there :)

Jiawei <jiawei@iscas.ac.cn>於 2023年6月7日 週三，20:57寫道：

> RISC-V Code Size Reduction(ZC*) extensions is a group of extensions
> which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
> extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]
>
> The implementation of the RISC-V Code Size Reduction extension in GCC is
> an important step towards making the RISC-V architecture more efficient.
>
> The cooperation with OpenHW group has played a crucial role in this effort,
> with facilitating the implementation, testing and validation. Currently
> works can also find in OpenHW group's github repo.[2]
>
> Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the
> specification, and Jeremy Bennett's patient guidance throughout the whole
> development process.a
>
> V2 changes:
> Fix Kito's comments in first version, Eswin assisted in optimizing the
> implementation of Zcmp extension:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617440.html
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617442.html
>
> https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620869.html
>
>
> [1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
>
> [2] github.com/openhwgroup/corev-gcc
>
> Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
> Co-Authored by: Simon Cook <simon.cook@embecosm.com>
> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
>
>   RISC-V: Minimal support for ZC extensions.
>   RISC-V: Enable compressible features when use ZC* extensions.
>   RISC-V: Add ZC* test for march args being passed.
>
>
> Jiawei (3):
>   RISC-V: Minimal support for ZC* extensions.
>   RISC-V: Enable compressible features when use ZC* extensions.
>   RISC-V: Add ZC* test for failed march args being passed.
>
>  gcc/common/config/riscv/riscv-common.cc   | 38 +++++++++++++++++++++++
>  gcc/config/riscv/riscv-c.cc               |  2 +-
>  gcc/config/riscv/riscv-opts.h             | 16 ++++++++++
>  gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +-
>  gcc/config/riscv/riscv.cc                 | 11 ++++---
>  gcc/config/riscv/riscv.h                  |  2 +-
>  gcc/config/riscv/riscv.opt                |  3 ++
>  gcc/testsuite/gcc.target/riscv/arch-22.c  |  5 +++
>  gcc/testsuite/gcc.target/riscv/arch-23.c  |  5 +++
>  9 files changed, 78 insertions(+), 7 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c
>
> --
> 2.25.1
>
>
  

Pushed to the trunk, with slight updates like rename and update testcases :)


On Wed, Jun 7, 2023 at 10:28 PM Kito Cheng via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Thanks Jiawei, v2 patch set are LGTM, but I would like to defer this until
> binutils part has merged, I know you guys already implement that for a
> while, so I think it’s almost there :)
>
> Jiawei <jiawei@iscas.ac.cn>於 2023年6月7日 週三，20:57寫道：
>
> > RISC-V Code Size Reduction(ZC*) extensions is a group of extensions
> > which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
> > extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]
> >
> > The implementation of the RISC-V Code Size Reduction extension in GCC is
> > an important step towards making the RISC-V architecture more efficient.
> >
> > The cooperation with OpenHW group has played a crucial role in this effort,
> > with facilitating the implementation, testing and validation. Currently
> > works can also find in OpenHW group's github repo.[2]
> >
> > Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the
> > specification, and Jeremy Bennett's patient guidance throughout the whole
> > development process.a
> >
> > V2 changes:
> > Fix Kito's comments in first version, Eswin assisted in optimizing the
> > implementation of Zcmp extension:
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617440.html
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617442.html
> >
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620869.html
> >
> >
> > [1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
> >
> > [2] github.com/openhwgroup/corev-gcc
> >
> > Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
> > Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
> > Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> > Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
> > Co-Authored by: Simon Cook <simon.cook@embecosm.com>
> > Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
> > Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
> >
> >   RISC-V: Minimal support for ZC extensions.
> >   RISC-V: Enable compressible features when use ZC* extensions.
> >   RISC-V: Add ZC* test for march args being passed.
> >
> >
> > Jiawei (3):
> >   RISC-V: Minimal support for ZC* extensions.
> >   RISC-V: Enable compressible features when use ZC* extensions.
> >   RISC-V: Add ZC* test for failed march args being passed.
> >
> >  gcc/common/config/riscv/riscv-common.cc   | 38 +++++++++++++++++++++++
> >  gcc/config/riscv/riscv-c.cc               |  2 +-
> >  gcc/config/riscv/riscv-opts.h             | 16 ++++++++++
> >  gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +-
> >  gcc/config/riscv/riscv.cc                 | 11 ++++---
> >  gcc/config/riscv/riscv.h                  |  2 +-
> >  gcc/config/riscv/riscv.opt                |  3 ++
> >  gcc/testsuite/gcc.target/riscv/arch-22.c  |  5 +++
> >  gcc/testsuite/gcc.target/riscv/arch-23.c  |  5 +++
> >  9 files changed, 78 insertions(+), 7 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c
> >
> > --
> > 2.25.1
> >
> >