From patchwork Wed Jun 7 12:56:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 70729 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8019F385B51F for ; Wed, 7 Jun 2023 12:57:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTPS id 23E32385773E for ; Wed, 7 Jun 2023 12:57:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 23E32385773E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.106.175.39]) by APP-01 (Coremail) with SMTP id qwCowADX3haXfoBkAQ8HDQ--.38410S3; Wed, 07 Jun 2023 20:57:00 +0800 (CST) From: Jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@dabbelt.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com, gaofei@eswincomputing.com, sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [PATCH v2 1/3] RISC-V: Minimal support for ZC* extensions. Date: Wed, 7 Jun 2023 20:56:39 +0800 Message-Id: <20230607125641.727633-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607125641.727633-1-jiawei@iscas.ac.cn> References: <20230607125641.727633-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowADX3haXfoBkAQ8HDQ--.38410S3 X-Coremail-Antispam: 1UD129KBjvJXoWxuw4UZF4DKFWxGr1DGF15Jwb_yoW7CryDpF s5Ca90v3yrWF43Wa1ftry8J34Ykw1Fgwn3JF4rZrW7AayDA3yrA3Z09343ur1kXFsYvrnF k3WUW34j9w4UGFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkIecxEwVAFjwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s02 6c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GF v_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvE c7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14 v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x 0pRItCwUUUUU= X-Originating-IP: [47.106.175.39] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiAwEPAGSAcK8jkwAAsG X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch is the minimal support for ZC* extensions, include the extension name, mask and target defination. Also define the dependencies with Zca and Zce extension. Notes that all ZC* extensions depend on the Zca extension. Zce includes all relevant ZC* extensions for microcontrollers using. Zce will imply zcf when 'f' extension enabled in rv32. Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Simon Cook Co-Authored by: Sinan Lin Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New extensions. * config/riscv/riscv-opts.h (MASK_ZCA): New mask. (MASK_ZCB): Ditto. (MASK_ZCE): Ditto. (MASK_ZCF): Ditto. (MASK_ZCD): Ditto. (MASK_ZCMP): Ditto. (MASK_ZCMT): Ditto. (TARGET_ZCA): New target. (TARGET_ZCB): Ditto. (TARGET_ZCE): Ditto. (TARGET_ZCF): Ditto. (TARGET_ZCD): Ditto. (TARGET_ZCMP): Ditto. (TARGET_ZCMT): Ditto. * config/riscv/riscv.opt: New target variable. --- gcc/common/config/riscv/riscv-common.cc | 38 +++++++++++++++++++++++++ gcc/config/riscv/riscv-opts.h | 16 +++++++++++ gcc/config/riscv/riscv.opt | 3 ++ 3 files changed, 57 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 3247d526c0a..89bdbef43a5 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -111,6 +111,16 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zhinx", "zhinxmin"}, {"zhinxmin", "zfinx"}, + {"zce", "zca"}, + {"zce", "zcb"}, + {"zce", "zcmp"}, + {"zce", "zcmt"}, + {"zcf", "zca"}, + {"zcd", "zca"}, + {"zcb", "zca"}, + {"zcmp", "zca"}, + {"zcmt", "zca"}, + {NULL, NULL} }; @@ -224,6 +234,14 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zca", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcb", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zce", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcf", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcd", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1156,8 +1174,19 @@ riscv_subset_list::parse (const char *arch, location_t loc) subset_list->handle_implied_ext (itr); } + /* Zce only implies zcf when RV32 and 'f' extension exist. */ + if (subset_list->lookup ("zce") != NULL + && subset_list->m_xlen == 32 + && subset_list->lookup ("f") != NULL + && subset_list->lookup ("zcf") == NULL) + subset_list->add ("zcf", false); + subset_list->handle_combine_ext (); + if (subset_list->lookup ("zcf") && subset_list->m_xlen == 64) + error_at (loc, "%<-march=%s%>: zcf extension supports in rv32 only" + , arch); + if (subset_list->lookup ("zfinx") && subset_list->lookup ("f")) error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point " "extensions", arch); @@ -1271,6 +1300,15 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL}, + /* Code-size reduction extensions. */ + {"zca", &gcc_options::x_riscv_zc_subext, MASK_ZCA}, + {"zcb", &gcc_options::x_riscv_zc_subext, MASK_ZCB}, + {"zce", &gcc_options::x_riscv_zc_subext, MASK_ZCE}, + {"zcf", &gcc_options::x_riscv_zc_subext, MASK_ZCF}, + {"zcd", &gcc_options::x_riscv_zc_subext, MASK_ZCD}, + {"zcmp", &gcc_options::x_riscv_zc_subext, MASK_ZCMP}, + {"zcmt", &gcc_options::x_riscv_zc_subext, MASK_ZCMT}, + {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 208a557b8ff..3429fc1218e 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -215,6 +215,22 @@ enum riscv_entity #define MASK_ZMMUL (1 << 0) #define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0) +#define MASK_ZCA (1 << 0) +#define MASK_ZCB (1 << 1) +#define MASK_ZCE (1 << 2) +#define MASK_ZCF (1 << 3) +#define MASK_ZCD (1 << 4) +#define MASK_ZCMP (1 << 5) +#define MASK_ZCMT (1 << 6) + +#define TARGET_ZCA ((riscv_zc_subext & MASK_ZCA) != 0) +#define TARGET_ZCB ((riscv_zc_subext & MASK_ZCB) != 0) +#define TARGET_ZCE ((riscv_zc_subext & MASK_ZCE) != 0) +#define TARGET_ZCF ((riscv_zc_subext & MASK_ZCF) != 0) +#define TARGET_ZCD ((riscv_zc_subext & MASK_ZCD) != 0) +#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0) +#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0) + #define MASK_SVINVAL (1 << 0) #define MASK_SVNAPOT (1 << 1) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 63d4710cb15..a6fdaef61cb 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -232,6 +232,9 @@ int riscv_zf_subext TargetVariable int riscv_zm_subext +TargetVariable +int riscv_zc_subext + TargetVariable int riscv_sv_subext From patchwork Wed Jun 7 12:56:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 70730 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7A7DC3856632 for ; Wed, 7 Jun 2023 12:57:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTPS id ACF503857727 for ; Wed, 7 Jun 2023 12:57:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ACF503857727 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.106.175.39]) by APP-01 (Coremail) with SMTP id qwCowADX3haXfoBkAQ8HDQ--.38410S4; Wed, 07 Jun 2023 20:57:01 +0800 (CST) From: Jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@dabbelt.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com, gaofei@eswincomputing.com, sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [PATCH v2 2/3] RISC-V: Enable compressible features when use ZC* extensions. Date: Wed, 7 Jun 2023 20:56:40 +0800 Message-Id: <20230607125641.727633-3-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607125641.727633-1-jiawei@iscas.ac.cn> References: <20230607125641.727633-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowADX3haXfoBkAQ8HDQ--.38410S4 X-Coremail-Antispam: 1UD129KBjvJXoWxXrWxAFyrJry5tw4fGw1xXwb_yoW7Jr1rpF Z8Gr4Fy34rArnxC3yft3W8G34Yyrn3Wa45Aws5Ar4UAan8XrZ7ZF1qkw4xA3WDXFZ5ZrZI kr40kFy5Aws8A3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY02Avz4vE174l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2Iq xVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r 4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY 6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aV AFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZE Xa7VUUOzVUUUUUU== X-Originating-IP: [47.106.175.39] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCQsPAGSAdOkYGQAAs1 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch enables the compressible features with ZC* extensions. Since all ZC* extension depends on the Zca extension, it's sufficient to only add the target Zca to extend the target RVC. Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Simon Cook gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Enable compressed builtins when ZC* extensions enabled. * config/riscv/riscv-shorten-memrefs.cc: Enable shorten_memrefs pass when ZC* extensions enabled. * config/riscv/riscv.cc (riscv_compressed_reg_p): Enable compressible registers when ZC* extensions enabled. (riscv_rtx_costs): Allow adjusting rtx costs when ZC* extensions enabled. (riscv_address_cost): Allow adjusting address cost when ZC* extensions enabled. (riscv_first_stack_step): Allow compression of the register saves without adding extra instructions. * config/riscv/riscv.h (FUNCTION_BOUNDARY): Adjusts function boundary to 16 bits when ZC* extensions enabled. --- gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv-shorten-memrefs.cc | 3 ++- gcc/config/riscv/riscv.cc | 11 +++++++---- gcc/config/riscv/riscv.h | 2 +- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 6ad562dcb8b..2937c160071 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) { builtin_define ("__riscv"); - if (TARGET_RVC) + if (TARGET_RVC || TARGET_ZCA) builtin_define ("__riscv_compressed"); if (TARGET_RVE) diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc b/gcc/config/riscv/riscv-shorten-memrefs.cc index 8f10d24ec39..6f2b973278e 100644 --- a/gcc/config/riscv/riscv-shorten-memrefs.cc +++ b/gcc/config/riscv/riscv-shorten-memrefs.cc @@ -65,7 +65,8 @@ public: /* opt_pass methods: */ virtual bool gate (function *) { - return TARGET_RVC && riscv_mshorten_memrefs && optimize > 0; + return (TARGET_RVC || TARGET_ZCA) + && riscv_mshorten_memrefs && optimize > 0; } virtual unsigned int execute (function *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 21e7d3b3caa..3a07122bf6a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1176,7 +1176,8 @@ static bool riscv_compressed_reg_p (int regno) { /* x8-x15/f8-f15 are compressible registers. */ - return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15) + return ((TARGET_RVC || TARGET_ZCA) + && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15) || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15))); } @@ -2416,7 +2417,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN /* When optimizing for size, make uncompressible 32-bit addresses more expensive so that compressible 32-bit addresses are preferred. */ - if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode + if ((TARGET_RVC || TARGET_ZCA) + && !speed && riscv_mshorten_memrefs && mode == SImode && !riscv_compressed_lw_address_p (XEXP (x, 0))) cost++; @@ -2828,7 +2830,8 @@ riscv_address_cost (rtx addr, machine_mode mode, { /* When optimizing for size, make uncompressible 32-bit addresses more * expensive so that compressible 32-bit addresses are preferred. */ - if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode + if ((TARGET_RVC || TARGET_ZCA) + && !speed && riscv_mshorten_memrefs && mode == SImode && !riscv_compressed_lw_address_p (addr)) return riscv_address_insns (addr, mode, false) + 1; return riscv_address_insns (addr, mode, false); @@ -5331,7 +5334,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame, poly_int64 remaining_siz && remaining_const_size % IMM_REACH >= min_first_step) return remaining_const_size % IMM_REACH; - if (TARGET_RVC) + if (TARGET_RVC || TARGET_ZCA) { /* If we need two subtracts, and one is small enough to allow compressed loads and stores, then put that one first. */ diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 4541255a8ae..a507db61900 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -186,7 +186,7 @@ ASM_MISA_SPEC #define PARM_BOUNDARY BITS_PER_WORD /* Allocation boundary (in *bits*) for the code of a function. */ -#define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32) +#define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32) /* The smallest supported stack boundary the calling convention supports. */ #define STACK_BOUNDARY \ From patchwork Wed Jun 7 12:56:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 70731 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 172BB3839056 for ; Wed, 7 Jun 2023 12:57:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTPS id D83173857725 for ; Wed, 7 Jun 2023 12:57:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D83173857725 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.106.175.39]) by APP-01 (Coremail) with SMTP id qwCowADX3haXfoBkAQ8HDQ--.38410S5; Wed, 07 Jun 2023 20:57:02 +0800 (CST) From: Jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@dabbelt.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com, gaofei@eswincomputing.com, sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [PATCH v2 3/3] RISC-V: Add ZC* test for failed march args being passed. Date: Wed, 7 Jun 2023 20:56:41 +0800 Message-Id: <20230607125641.727633-4-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607125641.727633-1-jiawei@iscas.ac.cn> References: <20230607125641.727633-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowADX3haXfoBkAQ8HDQ--.38410S5 X-Coremail-Antispam: 1UD129KBjvJXoW7Kr18JF1rtryxGryfXFWDJwb_yoW8Cr45pa nYkr4I9rWfGFZ7WFyYgFy7Xr4YqFsY9FWru3s2yw1Iy343tryDXFyktF43Kr1fJF4Uur13 Cw4v9w1Yvw4Fqr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY02Avz4vE174l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2Iq xVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r 4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY 6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aV AFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZE Xa7VUUwID7UUUUU== X-Originating-IP: [47.106.175.39] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiBwAPAGSAcUQiBgAAs9 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Add ZC* extensions march args tests for error input cases. Co-Authored by: Nandni Jamnadas Co-Authored by: Jiawei Co-Authored by: Mary Bennett Co-Authored by: Simon Cook gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-22.c: New test. * gcc.target/riscv/arch-23.c: New test. --- gcc/testsuite/gcc.target/riscv/arch-22.c | 5 +++++ gcc/testsuite/gcc.target/riscv/arch-23.c | 5 +++++ 2 files changed, 10 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c diff --git a/gcc/testsuite/gcc.target/riscv/arch-22.c b/gcc/testsuite/gcc.target/riscv/arch-22.c new file mode 100644 index 00000000000..3be4ade65a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-22.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */ +int foo() {} +/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-23.c b/gcc/testsuite/gcc.target/riscv/arch-23.c new file mode 100644 index 00000000000..cecce06e474 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-23.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64if_zce -mabi=lp64" } */ +int foo() {} +/* { dg-error "'-march=rv64if_zce': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64if_zca_zcb_zce_zcf_zcmp_zcmt': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */