mbox series

[v1,0/2] Basic support for the Ventana VT1 w/ instruction fusion

Message ID 20211114214757.3190803-1-philipp.tomsich@vrull.eu
Headers
Series Basic support for the Ventana VT1 w/ instruction fusion |

Message

Philipp Tomsich Nov. 14, 2021, 9:47 p.m. UTC 
  This series provides support for the Ventana VT1 (a 4-way superscalar
rv64gc_zba_zbb_zbc_zbs core) including support for the supported
instruction fusion patterns.

This includes the addition of the fusion-aware scheduling
infrastructure for RISC-V and implements idiom recognition for the
fusion patterns supported by VT1.


Philipp Tomsich (2):
  RISC-V: Add basic support for the Ventana-VT1 core
  RISC-V: Add instruction fusion (for ventana-vt1)

 gcc/config/riscv/riscv-cores.def |   2 +
 gcc/config/riscv/riscv-opts.h    |   3 +-
 gcc/config/riscv/riscv.c         | 210 +++++++++++++++++++++++++++++++
 gcc/config/riscv/riscv.md        |   2 +-
 gcc/doc/invoke.texi              |   4 +-
 5 files changed, 217 insertions(+), 4 deletions(-)

Comments

Kito Cheng Nov. 17, 2021, 2:05 p.m. UTC | #1 
Hi Philipp:

This patch set LGTM, feel free to commit once addressed those issues.

On Mon, Nov 15, 2021 at 5:48 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
>
> This series provides support for the Ventana VT1 (a 4-way superscalar
> rv64gc_zba_zbb_zbc_zbs core) including support for the supported
> instruction fusion patterns.
>
> This includes the addition of the fusion-aware scheduling
> infrastructure for RISC-V and implements idiom recognition for the
> fusion patterns supported by VT1.
>
>
> Philipp Tomsich (2):
>   RISC-V: Add basic support for the Ventana-VT1 core
>   RISC-V: Add instruction fusion (for ventana-vt1)
>
>  gcc/config/riscv/riscv-cores.def |   2 +
>  gcc/config/riscv/riscv-opts.h    |   3 +-
>  gcc/config/riscv/riscv.c         | 210 +++++++++++++++++++++++++++++++
>  gcc/config/riscv/riscv.md        |   2 +-
>  gcc/doc/invoke.texi              |   4 +-
>  5 files changed, 217 insertions(+), 4 deletions(-)
>
> --
> 2.32.0
>