diff mbox series

[3/7] aarch64: Fix sve2p1 extq instruction operands.

Message ID 20240522100439.1050296-5-srinath.parvathaneni@arm.com
State Superseded
Headers
Series aarch64: Fix the FEAT_SVE2p1 related issues. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Testing failed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

srinath May 22, 2024, 10:04 a.m. UTC 
  Hi,

This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands
count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th
argument an 4-bit unsigned immediate of extq instruction. The instruction encoding
is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately
precede in program order by a MOVPRFX instruction.

This issues was reported here:
 https://sourceware.org/pipermail/binutils/2024-February/132408.html

Regression testing for aarch64-none-elf target and found no regressions.

Ok for binutils master?

Regards,
Srinath.
---
 gas/config/tc-aarch64.c                      |  1 +
 gas/testsuite/gas/aarch64/sve2p1-1-bad.l     |  6 ------
 gas/testsuite/gas/aarch64/sve2p1-1.d         |  6 ------
 gas/testsuite/gas/aarch64/sve2p1-1.s         |  6 ------
 gas/testsuite/gas/aarch64/sve2p1-3-invalid.d |  3 +++
 gas/testsuite/gas/aarch64/sve2p1-3-invalid.l | 17 +++++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-3-invalid.s | 16 ++++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-3.d         | 20 ++++++++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-3.s         | 12 ++++++++++++
 include/opcode/aarch64.h                     |  1 +
 opcodes/aarch64-opc.c                        |  5 ++++-
 opcodes/aarch64-tbl.h                        |  4 +++-
 12 files changed, 77 insertions(+), 20 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3.s
diff mbox series

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 3f838cfd9a0..7029675a822 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6938,6 +6938,7 @@  parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_SVE_SIMM6:
 	case AARCH64_OPND_SVE_SIMM8:
 	case AARCH64_OPND_SVE_UIMM3:
+	case AARCH64_OPND_SVE_UIMM4:
 	case AARCH64_OPND_SVE_UIMM7:
 	case AARCH64_OPND_SVE_UIMM8:
 	case AARCH64_OPND_SVE_UIMM8_53:
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
index 4ea763f0e7d..718700e2ca2 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
@@ -41,12 +41,6 @@ 
 .*: Error: selected processor does not support `eorqv v4.2d,p3,z2.d'
 .*: Error: selected processor does not support `eorqv v8.2d,p4,z1.d'
 .*: Error: selected processor does not support `eorqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `extq z0.b,z0.b,z10.b\[15\]'
-.*: Error: selected processor does not support `extq z1.b,z1.b,z15.b\[7\]'
-.*: Error: selected processor does not support `extq z2.b,z2.b,z5.b\[3\]'
-.*: Error: selected processor does not support `extq z4.b,z4.b,z12.b\[1\]'
-.*: Error: selected processor does not support `extq z8.b,z8.b,z7.b\[4\]'
-.*: Error: selected processor does not support `extq z16.b,z16.b,z1.b\[8\]'
 .*: Error: selected processor does not support `faddqv v1.8h,p1,z8.h'
 .*: Error: selected processor does not support `faddqv v2.4s,p2,z4.s'
 .*: Error: selected processor does not support `faddqv v4.2d,p3,z2.d'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index 6afb051e67d..1c2e928685c 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -50,12 +50,6 @@ 
 .*:	04dd2c44 	eorqv	v4.2d, p3, z2.d
 .*:	04dd3028 	eorqv	v8.2d, p4, z1.d
 .*:	049d3c10 	eorqv	v16.4s, p7, z0.s
-.*:	056a27c0 	extq	z0.b, z0.b, z10.b\[15\]
-.*:	056f25c1 	extq	z1.b, z1.b, z15.b\[7\]
-.*:	056524c2 	extq	z2.b, z2.b, z5.b\[3\]
-.*:	056c2444 	extq	z4.b, z4.b, z12.b\[1\]
-.*:	05672508 	extq	z8.b, z8.b, z7.b\[4\]
-.*:	05612610 	extq	z16.b, z16.b, z1.b\[8\]
 .*:	6450a501 	faddqv	v1.8h, p1, z8.h
 .*:	6490a882 	faddqv	v2.4s, p2, z4.s
 .*:	64d0ac44 	faddqv	v4.2d, p3, z2.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s
index 08c777b2c70..5484557fb98 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.s
@@ -46,12 +46,6 @@  eorqv v4.2d, p3, z2.d
 eorqv v8.2d, p4, z1.d
 eorqv v16.4s, p7, z0.s
 
-extq z0.b, z0.b, z10.b[15]
-extq z1.b, z1.b, z15.b[7]
-extq z2.b, z2.b, z5.b[3]
-extq z4.b, z4.b, z12.b[1]
-extq z8.b, z8.b, z7.b[4]
-extq z16.b, z16.b, z1.b[8]
 faddqv v1.8h, p1, z8.h
 faddqv v2.4s, p2, z4.s
 faddqv v4.2d, p3, z2.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
new file mode 100644
index 00000000000..ff6ecb2027a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
@@ -0,0 +1,3 @@ 
+#name: Test of illegal SVE2.1 extq instructions.
+#as: -march=armv9.4-a
+#error_output: sve2p1-3-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
new file mode 100644
index 00000000000..ca8f4cda456
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
@@ -0,0 +1,17 @@ 
+.*: Assembler messages:
+.*: Error: operand mismatch -- `extq z0.b,z0.h,z0.b,#0'
+.*: Info:    did you mean this\?
+.*: Info:    	extq z0.b, z0.b, z0.b, #0
+.*: Error: operand 2 must be the same register as operand 1 -- `extq z31.b,z15.b,z0.b,#0'
+.*: Error: operand mismatch -- `extq z0.b,z0.b,z31.h,#0'
+.*: Info:    did you mean this\?
+.*: Info:    	extq z0.b, z0.b, z31.b, #0
+.*: Error: immediate value out of range 0 to 15 at operand 4 -- `extq z0.b,z0.b,z0.b,#16'
+.*: Error: operand mismatch -- `extq z0.h,z0.h,z0.h,#15'
+.*: Info:    did you mean this\?
+.*: Info:    	extq z0.b, z0.b, z0.b, #15
+.*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `extq z3.b,z3.b,z0.b,#0'
+.*: Error: operand 2 must be the same register as operand 1 -- `extq z31.b,z2.b,z0.b,#15'
+.*: Warning: instruction opens new dependency sequence without ending previous one -- `movprfx z31.b,p1/m,z10.b'
+.*: Warning: predicated instruction expected after `movprfx' -- `extq z31.b,z31.b,z0.b,#15'
+.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `extq z0.b,z0.b,z0.b,#0'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
new file mode 100644
index 00000000000..a6211ee24a0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
@@ -0,0 +1,16 @@ 
+extq z0.b, z0.h, z0.b, #0
+extq z31.b, z15.b, z0.b, #0
+extq z0.b, z0.b, z31.h, #0
+extq z0.b, z0.b, z0.b, #16
+extq z0.h, z0.h, z0.h, #15
+movprfx z1, z5
+extq z3.b, z3.b, z0.b, #0
+
+movprfx z31, z10
+extq z31.b, z2.b, z0.b, #15
+
+movprfx z31.b, p1/m, z10.b
+extq z31.b, z31.b, z0.b, #15
+
+movprfx z0, z2
+extq z0.b, z0.b, z0.b, #0
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3.d b/gas/testsuite/gas/aarch64/sve2p1-3.d
new file mode 100644
index 00000000000..bacb1b65bbe
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3.d
@@ -0,0 +1,20 @@ 
+#name: Test of SVE2.1 extq instructions.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	05602400 	extq	z0.b, z0.b, z0.b, #0
+.*:	0560241f 	extq	z31.b, z31.b, z0.b, #0
+.*:	056027e0 	extq	z0.b, z0.b, z31.b, #0
+.*:	056f2400 	extq	z0.b, z0.b, z0.b, #15
+.*:	056f27ff 	extq	z31.b, z31.b, z31.b, #15
+.*:	056727ef 	extq	z15.b, z15.b, z31.b, #7
+.*:	0420bca3 	movprfx	z3, z5
+.*:	05602403 	extq	z3.b, z3.b, z0.b, #0
+.*:	0420bd5f 	movprfx	z31, z10
+.*:	056f241f 	extq	z31.b, z31.b, z0.b, #15
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3.s b/gas/testsuite/gas/aarch64/sve2p1-3.s
new file mode 100644
index 00000000000..38864b791fa
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3.s
@@ -0,0 +1,12 @@ 
+extq z0.b, z0.b, z0.b, #0
+extq z31.b, z31.b, z0.b, #0
+extq z0.b, z0.b, z31.b, #0
+extq z0.b, z0.b, z0.b, #15
+extq z31.b, z31.b, z31.b, #15
+extq z15.b, z15.b, z31.b, #7
+
+movprfx z3, z5
+extq z3.b, z3.b, z0.b, #0
+
+movprfx z31, z10
+extq z31.b, z31.b, z0.b, #15
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 220ff68db88..f97a288d446 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -715,6 +715,7 @@  enum aarch64_opnd
   AARCH64_OPND_SVE_UIMM7,	/* SVE unsigned 7-bit immediate.  */
   AARCH64_OPND_SVE_UIMM8,	/* SVE unsigned 8-bit immediate.  */
   AARCH64_OPND_SVE_UIMM8_53,	/* SVE split unsigned 8-bit immediate.  */
+  AARCH64_OPND_SVE_UIMM4,	/* SVE unsigned 4-bit immediate.  */
   AARCH64_OPND_SVE_VZn,		/* Scalar SIMD&FP register in Zn field.  */
   AARCH64_OPND_SVE_Vd,		/* Scalar SIMD&FP register in Vd.  */
   AARCH64_OPND_SVE_Vm,		/* Scalar SIMD&FP register in Vm.  */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 032ab17e250..c4dd4ff9f49 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2697,6 +2697,7 @@  operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	case AARCH64_OPND_SVE_UIMM3:
 	case AARCH64_OPND_SVE_UIMM7:
 	case AARCH64_OPND_SVE_UIMM8:
+	case AARCH64_OPND_SVE_UIMM4:
 	case AARCH64_OPND_SVE_UIMM8_53:
 	case AARCH64_OPND_CSSC_UIMM8:
 	  size = get_operand_fields_width (get_operand_from_code (type));
@@ -4351,6 +4352,7 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SVE_UIMM3:
     case AARCH64_OPND_SVE_UIMM7:
     case AARCH64_OPND_SVE_UIMM8:
+    case AARCH64_OPND_SVE_UIMM4:
     case AARCH64_OPND_SVE_UIMM8_53:
     case AARCH64_OPND_IMM_ROT1:
     case AARCH64_OPND_IMM_ROT2:
@@ -5473,7 +5475,8 @@  verify_constraints (const struct aarch64_inst *inst,
 	     instruction for better error messages.  */
 	  if (!opcode->avariant
 	      || (!AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE)
-		  && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2)))
+		  && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2)
+		  && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2p1)))
 	    {
 	      mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
 	      mismatch_detail->error = _("SVE instruction expected after "
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 6ce42aed1e3..b6766e07e58 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6479,7 +6479,7 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
 
   SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
-  SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1),
+  SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
   SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
   SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
   SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
@@ -6986,6 +6986,8 @@  const struct aarch64_opcode aarch64_opcode_table[] =
       "an 8-bit unsigned immediate")					\
     Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3_10),		\
       "an 8-bit unsigned immediate")					\
+    Y(IMMEDIATE, imm, "SVE_UIMM4", 0, F(FLD_SVE_imm4),			\
+      "a 4-bit unsigned immediate")					\
     Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register")	\
     Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register")	\
     Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register")	\