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[0/2] Support Intel MOVRS related insns

Message ID 20241224092452.1825164-1-haochen.jiang@intel.com
Headers
Series Support Intel MOVRS related insns |

Message

Haochen Jiang Dec. 24, 2024, 9:24 a.m. UTC 
  Hi all,

These two patches will support MOVRS related insns, both of them are
mentioned in ISE055.

Ref: https://cdrdv2.intel.com/v1/dl/getContent/671368

MOVRS is actually composed of four parts, PREFETCHRST2, MOVRS,
MOVRS APX_F extension and MOVRS AVX10.2 extension. AMX-MOVRS patch
has once been sent out previously, with changes mentioned in the
mail.

In the previous AMX-MOVRS thread, there is an open on RS hint
placement. After discussion with Hardware design team, we found that
in vector space, we have VMOVNT*, where NT is cache hint and the size
comes after that. It actually aligns with current VMOVRS. So we should
not change the VMOVRS or it will lead to inconsistency in vector space,
which is a problem. On the other hand, the cache hint bundled together
also seems reasonable for those tile instructions and putting all of them
in front of the size would be less readable. Thus, the decision is no
change at the end of the day. We will accept the inconsistency between
vector instructions and tile instructions, but keep consistent within
vector instructions and within tile instructions.

Both of the patches got APX_F extensions, where the documentation did
not mention. I will mention that in the mail.

Ok for trunk?

Thx,
Haochen