From patchwork Tue Dec 24 09:24:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haochen Jiang X-Patchwork-Id: 103665 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DB68B3858C54 for ; Tue, 24 Dec 2024 09:28:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DB68B3858C54 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=iQzU2LOe X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by sourceware.org (Postfix) with ESMTPS id 785313858420 for ; Tue, 24 Dec 2024 09:24:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 785313858420 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 785313858420 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1735032299; cv=none; b=RbLqHYJC0JF46Tr0x3S3emrzrcc2bbVFyzybAYm3bA1bvQgZhgtdTJ25NA4GQroGLVd7UPy6BtcyZd0JAa3xMM3mkA/hapV8LnYT2WneJ4B6ZFu3LzwTquTxJM2fazfLjkb91sqxtfp6q5w7B0e09VTnDb3aLVRiHpPcbvekxaQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1735032299; c=relaxed/simple; bh=l5jnDOveJIGwmSOFs8QxEbzkgxc1xgCIO0FjiQbv2bo=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=G6K+l+9QtLosulPAh8q5agetobK1EiaLeDFymddvSqQOnWiR+A++C1Gn3jTUxtUGMh1l7+zpffKnx8G/K0kURLm1AkUQNjSPuKeET8KHg54a8VwG2NoIbVQsNENwShtAAFaEt7EYlcvnbxJGmPvsn+44GxKIHCMKcvnXyqoUy1I= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 785313858420 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1735032300; x=1766568300; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l5jnDOveJIGwmSOFs8QxEbzkgxc1xgCIO0FjiQbv2bo=; b=iQzU2LOeWI70QYrn28G6hg/IwERipW1tekUrJE4OVXfPpKohiv6e11WR 8QPK64iZqlSM8HdAgkCDV1Zg6gC7gFW5GBqelxM4UBCTMgSVvKK+PQ0mw dbu9lfrhJREadsZ6TKg8qxrKi7NYmRZufpfkeGaUtaMKkVDaToA9D3Z69 N8E4u2rg+Tn3rioKfWt9/rmOp1LYlSvJRy7/LH4KNSNOw/LYsRrAa3UkD 3vxr9aiSFAMWPs0Qtkpu7wKmsgvIXU7Y1YVGPPs7e+CIKpyJvweBdtMko ylzcomo79llKeXG1dmjT/HWF6tuNmHvUJrEHPLNmE6SXuRqB84AVPIxha g==; X-CSE-ConnectionGUID: QgjpPJnbQrSjl87+/wPONw== X-CSE-MsgGUID: C8R89CHqQKyk9nSWhyCd6A== X-IronPort-AV: E=McAfee;i="6700,10204,11295"; a="39180928" X-IronPort-AV: E=Sophos;i="6.12,259,1728975600"; d="scan'208";a="39180928" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Dec 2024 01:24:59 -0800 X-CSE-ConnectionGUID: G4PfXWrgTOSV5B+E7nmTyg== X-CSE-MsgGUID: UU0CgxRYRtGKHuDBaNgfoQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,259,1728975600"; d="scan'208";a="99526331" Received: from shliclel4217.sh.intel.com ([10.239.240.127]) by orviesa006.jf.intel.com with ESMTP; 24 Dec 2024 01:24:57 -0800 From: Haochen Jiang To: binutils@sourceware.org Cc: hjl.tools@gmail.com, jbeulich@suse.com, "Hu, Lin1" , Lili Cui Subject: [PATCH 1/2] Support Intel MOVRS Date: Tue, 24 Dec 2024 17:24:51 +0800 Message-Id: <20241224092452.1825164-2-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20241224092452.1825164-1-haochen.jiang@intel.com> References: <20241224092452.1825164-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: "Hu, Lin1" This patch focus on supporting MOVRS ISA. We could take this full ISA as four part: PREFETCHRST2, MOVRS, MOVRS APX_F extension and MOVRS AVX10.2 extension. The APX_F extension for MOVRS will be: - EVEX.LLZ.NP.MAP4.SCALABLE 8A !(11):rrr:bbb for r8/m8 with NF=0 and ND=0 - EVEX.LLZ.NP/66.MAP4.SCALABLE 8B !(11):rrr:bbb for rv/mv with NF=0 and ND=0 We did not merge the table together for APX_F since there is an explicit x64 for movrs insn. The current APX_F() did not support the combination between CPUIDs. gas/ChangeLog: * NEWS: Support Intel MOVRS. * config/tc-i386.c: Add MOVRS. * doc/c-i386.texi: Document .movrs. * testsuite/gas/i386/i386.exp: Run MOVRS tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Add MOVRS tests. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. * testsuite/gas/i386/lfence-load.d: Add prefetchrst2. * testsuite/gas/i386/lfence-load.s: Ditto. * testsuite/gas/i386/nops-8.d: Ditto. * testsuite/gas/i386/prefetch-intel.d: Ditto. * testsuite/gas/i386/prefetch.d: Ditto. * testsuite/gas/i386/x86-64-lfence-load.d: Ditto. * testsuite/gas/i386/x86-64-lfence-load.s: Ditto. * testsuite/gas/i386/x86-64-prefetch-intel.d: Ditto. * testsuite/gas/i386/x86-64-prefetch.d: Ditto. * testsuite/gas/i386/movrs-intel.d: New test. * testsuite/gas/i386/movrs-inval.l: Ditto. * testsuite/gas/i386/movrs-inval.s: Ditto. * testsuite/gas/i386/movrs.d: Ditto. * testsuite/gas/i386/movrs.s: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256.s: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512.s: Ditto. * testsuite/gas/i386/x86-64-movrs-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs.d: Ditto. * testsuite/gas/i386/x86-64-movrs.s: Ditto. * testsuite/gas/i386/x86-64-movrs-intel-suffix.d: Ditto. * testsuite/gas/i386/x86-64-movrs-suffix.d: Ditto. * testsuite/gas/i386/x86-64-movrs-suffix.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-mod.h: Add MOD_EVEX_MAP4_8A_W_0, MOD_EVEX_MAP4_8B. and MOD_EVEX_MAP5_6F. * i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP5_6F_M_0_X86_64. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8A. * i386-dis-evex-x86.h: Add X86_64_EVEX_MAP5_6F_M_0. * i386-dis-evex.h (evex_table): New entry for movrs. * i386-dis.c (MOD_0F18_REG_4): New. (MOD_0F388A): Ditto. (MOD_0F388B): Ditto. (MOD_EVEX_MAP4_8A_W_0): Ditto. (MOD_EVEX_MAP5_8B): Ditto. (MOD_EVEX_MAP5_6F): Ditto. (PREFIX_EVEX_MAP5_6F_M_0_X86_64): Ditto. (X86_64_0F388A_M_0): Ditto. (X86_64_0F388B_M_0): Ditto. (X86_64_EVEX_MAP5_6F_M_0): Ditto. (EVEX_W_MAP4_8A): Ditto. (three_byte_table): New entry for MOVRS. (reg_table): Ditto. (mod_table): Ditto. (x86_64_table): Ditto. Also include i386-dis-evex-x86.h. * i386-gen.c (cpu_flags): Add MOVRS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumovrs. * i386-opc.tbl: Add MOVRS instrctions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang Co-authored-by: Lili Cui --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 2 + gas/testsuite/gas/i386/i386.exp | 3 + gas/testsuite/gas/i386/lfence-load.d | 1 + gas/testsuite/gas/i386/lfence-load.s | 1 + gas/testsuite/gas/i386/movrs-intel.d | 15 + gas/testsuite/gas/i386/movrs-inval.l | 9 + gas/testsuite/gas/i386/movrs-inval.s | 12 + gas/testsuite/gas/i386/movrs.d | 13 + gas/testsuite/gas/i386/movrs.s | 15 + gas/testsuite/gas/i386/nops-8.d | 8 +- gas/testsuite/gas/i386/prefetch-intel.d | 2 +- gas/testsuite/gas/i386/prefetch.d | 2 +- .../gas/i386/x86-64-apx-evex-promoted-intel.d | 8 + .../gas/i386/x86-64-apx-evex-promoted-wig.d | 8 + .../gas/i386/x86-64-apx-evex-promoted.d | 8 + .../gas/i386/x86-64-apx-evex-promoted.s | 8 + gas/testsuite/gas/i386/x86-64-lfence-load.d | 1 + gas/testsuite/gas/i386/x86-64-lfence-load.s | 1 + .../gas/i386/x86-64-movrs-avx10_2-256-intel.d | 27 + .../gas/i386/x86-64-movrs-avx10_2-256.d | 25 + .../gas/i386/x86-64-movrs-avx10_2-256.s | 41 + .../gas/i386/x86-64-movrs-avx10_2-512-intel.d | 27 + .../gas/i386/x86-64-movrs-avx10_2-512.d | 25 + .../gas/i386/x86-64-movrs-avx10_2-512.s | 41 + gas/testsuite/gas/i386/x86-64-movrs-intel.d | 31 + .../gas/i386/x86-64-movrs-suffix-intel.d | 15 + gas/testsuite/gas/i386/x86-64-movrs-suffix.d | 13 + gas/testsuite/gas/i386/x86-64-movrs-suffix.s | 15 + gas/testsuite/gas/i386/x86-64-movrs.d | 29 + gas/testsuite/gas/i386/x86-64-movrs.s | 47 + .../gas/i386/x86-64-prefetch-intel.d | 2 +- gas/testsuite/gas/i386/x86-64-prefetch.d | 2 +- gas/testsuite/gas/i386/x86-64.exp | 6 + opcodes/i386-dis-evex-mod.h | 12 + opcodes/i386-dis-evex-prefix.h | 7 + opcodes/i386-dis-evex-w.h | 4 + opcodes/i386-dis-evex-x86-64.h | 5 + opcodes/i386-dis-evex.h | 6 +- opcodes/i386-dis.c | 46 +- opcodes/i386-gen.c | 1 + opcodes/i386-init.h | 764 +-- opcodes/i386-mnem.h | 4304 +++++++++-------- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 14 + opcodes/i386-tbl.h | 381 +- 47 files changed, 3330 insertions(+), 2683 deletions(-) create mode 100644 gas/testsuite/gas/i386/movrs-intel.d create mode 100644 gas/testsuite/gas/i386/movrs-inval.l create mode 100644 gas/testsuite/gas/i386/movrs-inval.s create mode 100644 gas/testsuite/gas/i386/movrs.d create mode 100644 gas/testsuite/gas/i386/movrs.s create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.d create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.s create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.d create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.s create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-suffix-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-suffix.d create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-suffix.s create mode 100644 gas/testsuite/gas/i386/x86-64-movrs.d create mode 100644 gas/testsuite/gas/i386/x86-64-movrs.s create mode 100644 opcodes/i386-dis-evex-x86-64.h diff --git a/gas/NEWS b/gas/NEWS index 51f2a97291b..a4ae3316102 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the x86 Intel MOVRS instructions. + * Add support for the x86 Intel AVX10.2 instructions. * Add support for the x86 Intel SM4 AVX10.2 instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index b18b5d7ed0d..31c367aadbc 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1225,6 +1225,7 @@ static const arch_entry cpu_arch[] = VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set), SUBARCH (gmi, GMI, GMI, false), SUBARCH (msr_imm, MSR_IMM, MSR_IMM, false), + SUBARCH (movrs, MOVRS, MOVRS, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index c29625d6ef3..47d5ec66140 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -224,6 +224,7 @@ accept various extension mnemonics. For example, @code{avx10.2/512}, @code{avx10.2/256}, @code{avx10.2/128}, +@code{movrs}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1699,6 +1700,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} @item @samp{.pbndkb} @tab @samp{.user_msr} @tab @samp{.msr_imm} @tab @samp{.avx10.2} +@item @samp{.movrs} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 9a310375123..4bd6478a296 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -541,6 +541,9 @@ if [gas_32_check] then { run_dump_test "avx10_2-512-sm4" run_dump_test "avx10_2-512-sm4-intel" run_list_test "avx10_2-sm4-inval" + run_dump_test "movrs" + run_dump_test "movrs-intel" + run_list_test "movrs-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/lfence-load.d b/gas/testsuite/gas/i386/lfence-load.d index a315be75254..4bed6001644 100644 --- a/gas/testsuite/gas/i386/lfence-load.d +++ b/gas/testsuite/gas/i386/lfence-load.d @@ -33,6 +33,7 @@ Disassembly of section .text: +[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%ebp\) +[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%ebp\) +[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%ebp\) + +[a-f0-9]+: 0f 18 65 00 prefetchrst2 0x0\(%ebp\) +[a-f0-9]+: 1f pop %ds +[a-f0-9]+: 0f ae e8 lfence +[a-f0-9]+: 9d popf diff --git a/gas/testsuite/gas/i386/lfence-load.s b/gas/testsuite/gas/i386/lfence-load.s index 4b4aa1610b3..157ee28f28b 100644 --- a/gas/testsuite/gas/i386/lfence-load.s +++ b/gas/testsuite/gas/i386/lfence-load.s @@ -20,6 +20,7 @@ _start: prefetcht1 (%ebp) prefetcht2 (%ebp) prefetchw (%ebp) + prefetchrst2 (%ebp) pop %ds popf popa diff --git a/gas/testsuite/gas/i386/movrs-intel.d b/gas/testsuite/gas/i386/movrs-intel.d new file mode 100644 index 00000000000..ae7f750711d --- /dev/null +++ b/gas/testsuite/gas/i386/movrs-intel.d @@ -0,0 +1,15 @@ +#objdump: -dw -Mintel +#name: i386 MOVRS insns (Intel disassembly) +#source: movrs.s + +.*: +file format .* + +Disassembly of section \.text: + +#... +[a-f0-9]+ <_intel>: +\s*[a-f0-9]+:\s*0f 18 a4 f4 00 00 00 10\s+prefetchrst2 BYTE PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*0f 18 21\s+prefetchrst2 BYTE PTR \[ecx\] +\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 BYTE PTR \[ecx\+0x7f\] +\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 BYTE PTR \[edx-0x80\] +#pass diff --git a/gas/testsuite/gas/i386/movrs-inval.l b/gas/testsuite/gas/i386/movrs-inval.l new file mode 100644 index 00000000000..43af5a158c1 --- /dev/null +++ b/gas/testsuite/gas/i386/movrs-inval.l @@ -0,0 +1,9 @@ +.* Assembler messages: +.*:5: Error: `movrs' is only supported in 64-bit mode +.*:6: Error: `movrs' is only supported in 64-bit mode +.*:7: Error: `movrs' is only supported in 64-bit mode +.*:8: Error: `movrs' is only supported in 64-bit mode +.*:9: Error: `vmovrsb' is only supported in 64-bit mode +.*:10: Error: `vmovrsd' is only supported in 64-bit mode +.*:11: Error: `vmovrsq' is only supported in 64-bit mode +.*:12: Error: `vmovrsw' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/movrs-inval.s b/gas/testsuite/gas/i386/movrs-inval.s new file mode 100644 index 00000000000..9236bf3d4eb --- /dev/null +++ b/gas/testsuite/gas/i386/movrs-inval.s @@ -0,0 +1,12 @@ +# Check Illegal 32bit MOVRS instructions + + .text +_start: + movrs 0x10000000(%esp, %esi, 8), %dx + movrs 0x10000000(%esp, %esi, 8), %edx + movrs 0x10000000(%esp, %esi, 8), %r12 + movrs 0x10000000(%esp, %esi, 8), %bl + vmovrsb 0x10000000(%esp, %esi, 8), %zmm6{%k7} + vmovrsd 0x10000000(%esp, %esi, 8), %zmm6{%k7} + vmovrsq 0x10000000(%esp, %esi, 8), %zmm6{%k7} + vmovrsw 0x10000000(%esp, %esi, 8), %zmm6{%k7} diff --git a/gas/testsuite/gas/i386/movrs.d b/gas/testsuite/gas/i386/movrs.d new file mode 100644 index 00000000000..5b2bb45b57c --- /dev/null +++ b/gas/testsuite/gas/i386/movrs.d @@ -0,0 +1,13 @@ +#objdump: -dw +#name: i386 MOVRS insns + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 18 a4 f4 00 00 00 10\s+prefetchrst2 0x10000000\(%esp,%esi,8\) +\s*[a-f0-9]+:\s*0f 18 21\s+prefetchrst2 \(%ecx\) +\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 0x7f\(%ecx\) +\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 -0x80\(%edx\) +#pass diff --git a/gas/testsuite/gas/i386/movrs.s b/gas/testsuite/gas/i386/movrs.s new file mode 100644 index 00000000000..e9592830296 --- /dev/null +++ b/gas/testsuite/gas/i386/movrs.s @@ -0,0 +1,15 @@ +# Check 32bit MOVRS instructions + + .text +_start: + prefetchrst2 0x10000000(%esp, %esi, 8) + prefetchrst2 (%ecx) + prefetchrst2 127(%ecx) + prefetchrst2 -128(%edx) + +_intel: + .intel_syntax noprefix + prefetchrst2 BYTE PTR [esp+esi*8+0x10000000] + prefetchrst2 BYTE PTR [ecx] + prefetchrst2 BYTE PTR [ecx+127] + prefetchrst2 BYTE PTR [edx-128] diff --git a/gas/testsuite/gas/i386/nops-8.d b/gas/testsuite/gas/i386/nops-8.d index 2d99ac7e51b..d0be54d2aac 100644 --- a/gas/testsuite/gas/i386/nops-8.d +++ b/gas/testsuite/gas/i386/nops-8.d @@ -74,7 +74,7 @@ Disassembly of section .text: +[a-f0-9]+: 0f 18 08 prefetcht0 \(%eax\) +[a-f0-9]+: 0f 18 10 prefetcht1 \(%eax\) +[a-f0-9]+: 0f 18 18 prefetcht2 \(%eax\) - +[a-f0-9]+: 0f 18 20 nopl \(%eax\) + +[a-f0-9]+: 0f 18 20 prefetchrst2 \(%eax\) +[a-f0-9]+: 0f 18 28 nopl \(%eax\) +[a-f0-9]+: 0f 18 30 nopl \(%eax\) +[a-f0-9]+: 0f 18 38 nopl \(%eax\) @@ -146,7 +146,7 @@ Disassembly of section .text: +[a-f0-9]+: 66 0f 18 08 data16 prefetcht0 \(%eax\) +[a-f0-9]+: 66 0f 18 10 data16 prefetcht1 \(%eax\) +[a-f0-9]+: 66 0f 18 18 data16 prefetcht2 \(%eax\) - +[a-f0-9]+: 66 0f 18 20 nopw \(%eax\) + +[a-f0-9]+: 66 0f 18 20 data16 prefetchrst2 \(%eax\) +[a-f0-9]+: 66 0f 18 28 nopw \(%eax\) +[a-f0-9]+: 66 0f 18 30 nopw \(%eax\) +[a-f0-9]+: 66 0f 18 38 nopw \(%eax\) @@ -218,7 +218,7 @@ Disassembly of section .text: +[a-f0-9]+: f3 0f 18 08 repz prefetcht0 \(%eax\) +[a-f0-9]+: f3 0f 18 10 repz prefetcht1 \(%eax\) +[a-f0-9]+: f3 0f 18 18 repz prefetcht2 \(%eax\) - +[a-f0-9]+: f3 0f 18 20 repz nopl \(%eax\) + +[a-f0-9]+: f3 0f 18 20 repz prefetchrst2 \(%eax\) +[a-f0-9]+: f3 0f 18 28 repz nopl \(%eax\) +[a-f0-9]+: f3 0f 18 30 repz nopl \(%eax\) +[a-f0-9]+: f3 0f 18 38 repz nopl \(%eax\) @@ -290,7 +290,7 @@ Disassembly of section .text: +[a-f0-9]+: f2 0f 18 08 repnz prefetcht0 \(%eax\) +[a-f0-9]+: f2 0f 18 10 repnz prefetcht1 \(%eax\) +[a-f0-9]+: f2 0f 18 18 repnz prefetcht2 \(%eax\) - +[a-f0-9]+: f2 0f 18 20 repnz nopl \(%eax\) + +[a-f0-9]+: f2 0f 18 20 repnz prefetchrst2 \(%eax\) +[a-f0-9]+: f2 0f 18 28 repnz nopl \(%eax\) +[a-f0-9]+: f2 0f 18 30 repnz nopl \(%eax\) +[a-f0-9]+: f2 0f 18 38 repnz nopl \(%eax\) diff --git a/gas/testsuite/gas/i386/prefetch-intel.d b/gas/testsuite/gas/i386/prefetch-intel.d index ca0fd914515..1a6fad15c73 100644 --- a/gas/testsuite/gas/i386/prefetch-intel.d +++ b/gas/testsuite/gas/i386/prefetch-intel.d @@ -22,7 +22,7 @@ Disassembly of section .text: \s*[a-f0-9]+: 0f 18 08 prefetcht0 BYTE PTR \[eax\] \s*[a-f0-9]+: 0f 18 10 prefetcht1 BYTE PTR \[eax\] \s*[a-f0-9]+: 0f 18 18 prefetcht2 BYTE PTR \[eax\] -\s*[a-f0-9]+: 0f 18 20 nop DWORD PTR \[eax\] +\s*[a-f0-9]+: 0f 18 20 prefetchrst2 BYTE PTR \[eax\] \s*[a-f0-9]+: 0f 18 28 nop DWORD PTR \[eax\] \s*[a-f0-9]+: 0f 18 30 nop DWORD PTR \[eax\] \s*[a-f0-9]+: 0f 18 38 nop DWORD PTR \[eax\] diff --git a/gas/testsuite/gas/i386/prefetch.d b/gas/testsuite/gas/i386/prefetch.d index 285077862a7..f46c1410e94 100644 --- a/gas/testsuite/gas/i386/prefetch.d +++ b/gas/testsuite/gas/i386/prefetch.d @@ -21,7 +21,7 @@ Disassembly of section .text: \s*[a-f0-9]+: 0f 18 08 prefetcht0 \(%eax\) \s*[a-f0-9]+: 0f 18 10 prefetcht1 \(%eax\) \s*[a-f0-9]+: 0f 18 18 prefetcht2 \(%eax\) -\s*[a-f0-9]+: 0f 18 20 nopl \(%eax\) +\s*[a-f0-9]+: 0f 18 20 prefetchrst2 \(%eax\) \s*[a-f0-9]+: 0f 18 28 nopl \(%eax\) \s*[a-f0-9]+: 0f 18 30 nopl \(%eax\) \s*[a-f0-9]+: 0f 18 38 nopl \(%eax\) diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d index 50ddd5d71a8..a45711c5b4b 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d @@ -118,6 +118,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+r31,\[r31\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],r25d [ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r31 +[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+r16b,BYTE PTR \[r31\+rax\*4\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+r18w,WORD PTR \[r16\+rax\*4\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+r25d,DWORD PTR \[r31\+rax\*4\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+r31,QWORD PTR \[r16\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+r10d,edx,r25d [ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+r11,r15,r31 [ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+edx,r25d,DWORD PTR \[r31\+rax\*4\+0x123\] @@ -253,6 +257,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+r31,\[r31\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],r25d [ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r31 +[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+r16b,BYTE PTR \[r31\+rax\*4\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+r18w,WORD PTR \[r16\+rax\*4\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+r25d,DWORD PTR \[r31\+rax\*4\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+r31,QWORD PTR \[r16\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+r10d,edx,r25d [ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+r11,r15,r31 [ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+edx,r25d,DWORD PTR \[r31\+rax\*4\+0x123\] diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d index 7451ca1b95e..50a406cbfa6 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d @@ -118,6 +118,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 4c .d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\) +[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b +[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w +[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d +[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31 [ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d [ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11 [ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx @@ -253,6 +257,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 4c .d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\) +[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b +[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w +[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d +[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31 [ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d [ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11 [ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d index b8976db0914..3e5938ab019 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d @@ -118,6 +118,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\) +[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b +[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w +[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d +[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31 [ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d [ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11 [ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx @@ -253,6 +257,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\) +[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b +[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w +[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d +[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31 [ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d [ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11 [ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s index 7880f66fb26..bcac9caff7b 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s @@ -112,6 +112,10 @@ _start: movdir64b 0x123(%r31,%rax,4),%r31 movdiri %r25d,0x123(%r31,%rax,4) movdiri %r31,0x123(%r31,%rax,4) + movrs 0x123(%r31,%rax,4),%r16b + movrs 0x123(%r16,%rax,4),%r18w + movrs 0x123(%r31,%rax,4),%r25d + movrs 0x123(%r16,%rax,4),%r31 pdep %r25d,%edx,%r10d pdep %r31,%r15,%r11 pdep 0x123(%r31,%rax,4),%r25d,%edx @@ -249,6 +253,10 @@ _start: movdir64b r31,[r31+rax*4+0x123] movdiri DWORD PTR [r31+rax*4+0x123],r25d movdiri QWORD PTR [r31+rax*4+0x123],r31 + movrs r16b,BYTE PTR [r31+rax*4+0x123] + movrs r18w,WORD PTR [r16+rax*4+0x123] + movrs r25d,DWORD PTR [r31+rax*4+0x123] + movrs r31,QWORD PTR [r16+rax*4+0x123] pdep r10d,edx,r25d pdep r11,r15,r31 pdep edx,r25d,DWORD PTR [r31+rax*4+0x123] diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.d b/gas/testsuite/gas/i386/x86-64-lfence-load.d index dcfa810a513..c86155ec516 100644 --- a/gas/testsuite/gas/i386/x86-64-lfence-load.d +++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d @@ -35,6 +35,7 @@ Disassembly of section .text: +[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\) +[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> +[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> + +[a-f0-9]+: 0f 18 65 00 prefetchrst2 0x0\(%rbp\) +[a-f0-9]+: 0f a1 pop %fs +[a-f0-9]+: 0f ae e8 lfence +[a-f0-9]+: 9d popf diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.s b/gas/testsuite/gas/i386/x86-64-lfence-load.s index 05c07adc189..e30b9a49800 100644 --- a/gas/testsuite/gas/i386/x86-64-lfence-load.s +++ b/gas/testsuite/gas/i386/x86-64-lfence-load.s @@ -22,6 +22,7 @@ _start: prefetchw (%rbp) prefetchit0 0x12345678(%rip) prefetchit1 0x12345678(%rip) + prefetchrst2 (%rbp) pop %fs popf xlatb (%rbx) diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d new file mode 100644 index 00000000000..fbbc85f603e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d @@ -0,0 +1,27 @@ +#objdump: -dw -Mintel +#name: x86_64 MOVRS, AVX10.2/256 insns (Intel disassembly) +#source: x86-64-movrs-avx10_2-256.s + +.*: +file format .* + +Disassembly of section \.text: + +#... +[a-f0-9]+ <_intel>: +\s*[a-f0-9]+:\s*62 25 7f 0f 6f b4 f5 00 00 00 10\s+vmovrsb xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*62 45 7f 08 6f 31\s+vmovrsb xmm30,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*62 65 7f 08 6f 71 7f\s+vmovrsb xmm30,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*62 65 7f 8f 6f 72 80\s+vmovrsb xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\] +\s*[a-f0-9]+:\s*62 25 7e 0f 6f b4 f5 00 00 00 10\s+vmovrsd xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*62 45 7e 08 6f 31\s+vmovrsd xmm30,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*62 65 7e 08 6f 71 7f\s+vmovrsd xmm30,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*62 65 7e 8f 6f 72 80\s+vmovrsd xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\] +\s*[a-f0-9]+:\s*62 25 fe 0f 6f b4 f5 00 00 00 10\s+vmovrsq xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*62 45 fe 08 6f 31\s+vmovrsq xmm30,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*62 65 fe 08 6f 71 7f\s+vmovrsq xmm30,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*62 65 fe 8f 6f 72 80\s+vmovrsq xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\] +\s*[a-f0-9]+:\s*62 25 ff 0f 6f b4 f5 00 00 00 10\s+vmovrsw xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*62 45 ff 08 6f 31\s+vmovrsw xmm30,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*62 65 ff 08 6f 71 7f\s+vmovrsw xmm30,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*62 65 ff 8f 6f 72 80\s+vmovrsw xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.d b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.d new file mode 100644 index 00000000000..68b38be6aa6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.d @@ -0,0 +1,25 @@ +#objdump: -dw +#name: x86_64 MOVRS, AVX10.2/256 insns + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 25 7f 0f 6f b4 f5 00 00 00 10\s+vmovrsb 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\} +\s*[a-f0-9]+:\s*62 45 7f 08 6f 31\s+vmovrsb \(%r9\),%xmm30 +\s*[a-f0-9]+:\s*62 65 7f 08 6f 71 7f\s+vmovrsb 0x7f0\(%rcx\),%xmm30 +\s*[a-f0-9]+:\s*62 65 7f 8f 6f 72 80\s+vmovrsb -0x800\(%rdx\),%xmm30\{%k7\}\{z\} +\s*[a-f0-9]+:\s*62 25 7e 0f 6f b4 f5 00 00 00 10\s+vmovrsd 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\} +\s*[a-f0-9]+:\s*62 45 7e 08 6f 31\s+vmovrsd \(%r9\),%xmm30 +\s*[a-f0-9]+:\s*62 65 7e 08 6f 71 7f\s+vmovrsd 0x7f0\(%rcx\),%xmm30 +\s*[a-f0-9]+:\s*62 65 7e 8f 6f 72 80\s+vmovrsd -0x800\(%rdx\),%xmm30\{%k7\}\{z\} +\s*[a-f0-9]+:\s*62 25 fe 0f 6f b4 f5 00 00 00 10\s+vmovrsq 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\} +\s*[a-f0-9]+:\s*62 45 fe 08 6f 31\s+vmovrsq \(%r9\),%xmm30 +\s*[a-f0-9]+:\s*62 65 fe 08 6f 71 7f\s+vmovrsq 0x7f0\(%rcx\),%xmm30 +\s*[a-f0-9]+:\s*62 65 fe 8f 6f 72 80\s+vmovrsq -0x800\(%rdx\),%xmm30\{%k7\}\{z\} +\s*[a-f0-9]+:\s*62 25 ff 0f 6f b4 f5 00 00 00 10\s+vmovrsw 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\} +\s*[a-f0-9]+:\s*62 45 ff 08 6f 31\s+vmovrsw \(%r9\),%xmm30 +\s*[a-f0-9]+:\s*62 65 ff 08 6f 71 7f\s+vmovrsw 0x7f0\(%rcx\),%xmm30 +\s*[a-f0-9]+:\s*62 65 ff 8f 6f 72 80\s+vmovrsw -0x800\(%rdx\),%xmm30\{%k7\}\{z\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.s b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.s new file mode 100644 index 00000000000..c699d8e3d75 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.s @@ -0,0 +1,41 @@ +# Check 64bit MOVRS, AVX10.2/256 instructions + + .arch generic64 + .arch .avx10.2/256 + .arch .movrs +_start: + vmovrsb 0x10000000(%rbp, %r14, 8), %xmm30{%k7} + vmovrsb (%r9), %xmm30 + vmovrsb 2032(%rcx), %xmm30 + vmovrsb -2048(%rdx), %xmm30{%k7}{z} + vmovrsd 0x10000000(%rbp, %r14, 8), %xmm30{%k7} + vmovrsd (%r9), %xmm30 + vmovrsd 2032(%rcx), %xmm30 + vmovrsd -2048(%rdx), %xmm30{%k7}{z} + vmovrsq 0x10000000(%rbp, %r14, 8), %xmm30{%k7} + vmovrsq (%r9), %xmm30 + vmovrsq 2032(%rcx), %xmm30 + vmovrsq -2048(%rdx), %xmm30{%k7}{z} + vmovrsw 0x10000000(%rbp, %r14, 8), %xmm30{%k7} + vmovrsw (%r9), %xmm30 + vmovrsw 2032(%rcx), %xmm30 + vmovrsw -2048(%rdx), %xmm30{%k7}{z} + +_intel: + .intel_syntax noprefix + vmovrsb xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000] + vmovrsb xmm30, XMMWORD PTR [r9] + vmovrsb xmm30, XMMWORD PTR [rcx+2032] + vmovrsb xmm30{k7}{z}, XMMWORD PTR [rdx-2048] + vmovrsd xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000] + vmovrsd xmm30, XMMWORD PTR [r9] + vmovrsd xmm30, XMMWORD PTR [rcx+2032] + vmovrsd xmm30{k7}{z}, XMMWORD PTR [rdx-2048] + vmovrsq xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000] + vmovrsq xmm30, XMMWORD PTR [r9] + vmovrsq xmm30, XMMWORD PTR [rcx+2032] + vmovrsq xmm30{k7}{z}, XMMWORD PTR [rdx-2048] + vmovrsw xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000] + vmovrsw xmm30, XMMWORD PTR [r9] + vmovrsw xmm30, XMMWORD PTR [rcx+2032] + vmovrsw xmm30{k7}{z}, XMMWORD PTR [rdx-2048] diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d new file mode 100644 index 00000000000..e2f5847172a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d @@ -0,0 +1,27 @@ +#objdump: -dw -Mintel +#name: x86_64 MOVRS, AVX10.2/512 insns (Intel disassembly) +#source: x86-64-movrs-avx10_2-512.s + +.*: +file format .* + +Disassembly of section \.text: + +#... +[a-f0-9]+ <_intel>: +\s*[a-f0-9]+:\s*62 25 7f 4f 6f b4 f5 00 00 00 10\s+vmovrsb zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*62 45 7f 48 6f 31\s+vmovrsb zmm30,ZMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*62 65 7f 48 6f 71 7f\s+vmovrsb zmm30,ZMMWORD PTR \[rcx\+0x1fc0\] +\s*[a-f0-9]+:\s*62 65 7f cf 6f 72 80\s+vmovrsb zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\] +\s*[a-f0-9]+:\s*62 25 7e 4f 6f b4 f5 00 00 00 10\s+vmovrsd zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*62 45 7e 48 6f 31\s+vmovrsd zmm30,ZMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*62 65 7e 48 6f 71 7f\s+vmovrsd zmm30,ZMMWORD PTR \[rcx\+0x1fc0\] +\s*[a-f0-9]+:\s*62 65 7e cf 6f 72 80\s+vmovrsd zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\] +\s*[a-f0-9]+:\s*62 25 fe 4f 6f b4 f5 00 00 00 10\s+vmovrsq zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*62 45 fe 48 6f 31\s+vmovrsq zmm30,ZMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*62 65 fe 48 6f 71 7f\s+vmovrsq zmm30,ZMMWORD PTR \[rcx\+0x1fc0\] +\s*[a-f0-9]+:\s*62 65 fe cf 6f 72 80\s+vmovrsq zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\] +\s*[a-f0-9]+:\s*62 25 ff 4f 6f b4 f5 00 00 00 10\s+vmovrsw zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*62 45 ff 48 6f 31\s+vmovrsw zmm30,ZMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*62 65 ff 48 6f 71 7f\s+vmovrsw zmm30,ZMMWORD PTR \[rcx\+0x1fc0\] +\s*[a-f0-9]+:\s*62 65 ff cf 6f 72 80\s+vmovrsw zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.d b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.d new file mode 100644 index 00000000000..af32491c2e6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.d @@ -0,0 +1,25 @@ +#objdump: -dw +#name: x86_64 MOVRS, AVX10.2/512 insns + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 25 7f 4f 6f b4 f5 00 00 00 10\s+vmovrsb 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\} +\s*[a-f0-9]+:\s*62 45 7f 48 6f 31\s+vmovrsb \(%r9\),%zmm30 +\s*[a-f0-9]+:\s*62 65 7f 48 6f 71 7f\s+vmovrsb 0x1fc0\(%rcx\),%zmm30 +\s*[a-f0-9]+:\s*62 65 7f cf 6f 72 80\s+vmovrsb -0x2000\(%rdx\),%zmm30\{%k7\}\{z\} +\s*[a-f0-9]+:\s*62 25 7e 4f 6f b4 f5 00 00 00 10\s+vmovrsd 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\} +\s*[a-f0-9]+:\s*62 45 7e 48 6f 31\s+vmovrsd \(%r9\),%zmm30 +\s*[a-f0-9]+:\s*62 65 7e 48 6f 71 7f\s+vmovrsd 0x1fc0\(%rcx\),%zmm30 +\s*[a-f0-9]+:\s*62 65 7e cf 6f 72 80\s+vmovrsd -0x2000\(%rdx\),%zmm30\{%k7\}\{z\} +\s*[a-f0-9]+:\s*62 25 fe 4f 6f b4 f5 00 00 00 10\s+vmovrsq 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\} +\s*[a-f0-9]+:\s*62 45 fe 48 6f 31\s+vmovrsq \(%r9\),%zmm30 +\s*[a-f0-9]+:\s*62 65 fe 48 6f 71 7f\s+vmovrsq 0x1fc0\(%rcx\),%zmm30 +\s*[a-f0-9]+:\s*62 65 fe cf 6f 72 80\s+vmovrsq -0x2000\(%rdx\),%zmm30\{%k7\}\{z\} +\s*[a-f0-9]+:\s*62 25 ff 4f 6f b4 f5 00 00 00 10\s+vmovrsw 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\} +\s*[a-f0-9]+:\s*62 45 ff 48 6f 31\s+vmovrsw \(%r9\),%zmm30 +\s*[a-f0-9]+:\s*62 65 ff 48 6f 71 7f\s+vmovrsw 0x1fc0\(%rcx\),%zmm30 +\s*[a-f0-9]+:\s*62 65 ff cf 6f 72 80\s+vmovrsw -0x2000\(%rdx\),%zmm30\{%k7\}\{z\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.s b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.s new file mode 100644 index 00000000000..5caaf4f5097 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.s @@ -0,0 +1,41 @@ +# Check 64bit MOVRS, AVX10.2/512 instructions + + .arch generic64 + .arch .avx10.2/512 + .arch .movrs +_start: + vmovrsb 0x10000000(%rbp, %r14, 8), %zmm30{%k7} + vmovrsb (%r9), %zmm30 + vmovrsb 8128(%rcx), %zmm30 + vmovrsb -8192(%rdx), %zmm30{%k7}{z} + vmovrsd 0x10000000(%rbp, %r14, 8), %zmm30{%k7} + vmovrsd (%r9), %zmm30 + vmovrsd 8128(%rcx), %zmm30 + vmovrsd -8192(%rdx), %zmm30{%k7}{z} + vmovrsq 0x10000000(%rbp, %r14, 8), %zmm30{%k7} + vmovrsq (%r9), %zmm30 + vmovrsq 8128(%rcx), %zmm30 + vmovrsq -8192(%rdx), %zmm30{%k7}{z} + vmovrsw 0x10000000(%rbp, %r14, 8), %zmm30{%k7} + vmovrsw (%r9), %zmm30 + vmovrsw 8128(%rcx), %zmm30 + vmovrsw -8192(%rdx), %zmm30{%k7}{z} + +_intel: + .intel_syntax noprefix + vmovrsb zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000] + vmovrsb zmm30, ZMMWORD PTR [r9] + vmovrsb zmm30, ZMMWORD PTR [rcx+8128] + vmovrsb zmm30{k7}{z}, ZMMWORD PTR [rdx-8192] + vmovrsd zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000] + vmovrsd zmm30, ZMMWORD PTR [r9] + vmovrsd zmm30, ZMMWORD PTR [rcx+8128] + vmovrsd zmm30{k7}{z}, ZMMWORD PTR [rdx-8192] + vmovrsq zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000] + vmovrsq zmm30, ZMMWORD PTR [r9] + vmovrsq zmm30, ZMMWORD PTR [rcx+8128] + vmovrsq zmm30{k7}{z}, ZMMWORD PTR [rdx-8192] + vmovrsw zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000] + vmovrsw zmm30, ZMMWORD PTR [r9] + vmovrsw zmm30, ZMMWORD PTR [rcx+8128] + vmovrsw zmm30{k7}{z}, ZMMWORD PTR [rdx-8192] diff --git a/gas/testsuite/gas/i386/x86-64-movrs-intel.d b/gas/testsuite/gas/i386/x86-64-movrs-intel.d new file mode 100644 index 00000000000..145644f8209 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-intel.d @@ -0,0 +1,31 @@ +#objdump: -dw -Mintel +#name: x86_64 MOVRS insns (Intel disassembly) +#source: x86-64-movrs.s + +.*: +file format .* + +Disassembly of section \.text: + +#... +[a-f0-9]+ <_intel>: +\s*[a-f0-9]+:\s*66 42 0f 38 8b 94 f5 00 00 00 10\s+movrs dx,WORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*66 41 0f 38 8b 11\s+movrs dx,WORD PTR \[r9\] +\s*[a-f0-9]+:\s*66 0f 38 8b 91 fe 00 00 00\s+movrs dx,WORD PTR \[rcx\+0xfe\] +\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrs dx,WORD PTR \[rdx-0x100\] +\s*[a-f0-9]+:\s*42 0f 38 8b 94 f5 00 00 00 10\s+movrs edx,DWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*41 0f 38 8b 11\s+movrs edx,DWORD PTR \[r9\] +\s*[a-f0-9]+:\s*0f 38 8b 91 fc 01 00 00\s+movrs edx,DWORD PTR \[rcx\+0x1fc\] +\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrs edx,DWORD PTR \[rdx-0x200\] +\s*[a-f0-9]+:\s*4e 0f 38 8b a4 f5 00 00 00 10\s+movrs r12,QWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*4d 0f 38 8b 21\s+movrs r12,QWORD PTR \[r9\] +\s*[a-f0-9]+:\s*4c 0f 38 8b a1 f8 03 00 00\s+movrs r12,QWORD PTR \[rcx\+0x3f8\] +\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrs r12,QWORD PTR \[rdx-0x400\] +\s*[a-f0-9]+:\s*42 0f 38 8a 9c f5 00 00 00 10\s+movrs bl,BYTE PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*41 0f 38 8a 19\s+movrs bl,BYTE PTR \[r9\] +\s*[a-f0-9]+:\s*0f 38 8a 59 7f\s+movrs bl,BYTE PTR \[rcx\+0x7f\] +\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrs bl,BYTE PTR \[rdx-0x80\] +\s*[a-f0-9]+:\s*42 0f 18 a4 f5 00 00 00 10\s+prefetchrst2 BYTE PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*41 0f 18 21\s+prefetchrst2 BYTE PTR \[r9\] +\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 BYTE PTR \[rcx\+0x7f\] +\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 BYTE PTR \[rdx-0x80\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-movrs-suffix-intel.d b/gas/testsuite/gas/i386/x86-64-movrs-suffix-intel.d new file mode 100644 index 00000000000..b1dcb2db898 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-suffix-intel.d @@ -0,0 +1,15 @@ +#objdump: -dwMsuffix -Mintel +#name: x86_64 MOVRS insns +#source: x86-64-movrs-suffix.s + +.*: +file format .* + +Disassembly of section \.text: + +#... +[a-f0-9]+ <_intel>: +\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrsw -0x100\(%rdx\),%dx +\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrsl -0x200\(%rdx\),%edx +\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrsq -0x400\(%rdx\),%r12 +\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrsb -0x80\(%rdx\),%bl +#pass diff --git a/gas/testsuite/gas/i386/x86-64-movrs-suffix.d b/gas/testsuite/gas/i386/x86-64-movrs-suffix.d new file mode 100644 index 00000000000..7f71b1dfbd0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-suffix.d @@ -0,0 +1,13 @@ +#objdump: -dwMsuffix +#name: x86_64 MOVRS insns + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrsw -0x100\(%rdx\),%dx +\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrsl -0x200\(%rdx\),%edx +\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrsq -0x400\(%rdx\),%r12 +\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrsb -0x80\(%rdx\),%bl +#pass diff --git a/gas/testsuite/gas/i386/x86-64-movrs-suffix.s b/gas/testsuite/gas/i386/x86-64-movrs-suffix.s new file mode 100644 index 00000000000..6120b768d7c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs-suffix.s @@ -0,0 +1,15 @@ +# Check 64bit MOVRS instructions + + .text +_start: + movrsw -256(%rdx), %dx + movrsl -512(%rdx), %edx + movrsq -1024(%rdx), %r12 + movrsb -128(%rdx), %bl + +_intel: + .intel_syntax noprefix + movrsw dx, WORD PTR [rdx-256] + movrsl edx, DWORD PTR [rdx-512] + movrsq r12, QWORD PTR [rdx-1024] + movrsb bl, BYTE PTR [rdx-128] diff --git a/gas/testsuite/gas/i386/x86-64-movrs.d b/gas/testsuite/gas/i386/x86-64-movrs.d new file mode 100644 index 00000000000..b5d48cd4fe0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs.d @@ -0,0 +1,29 @@ +#objdump: -dw +#name: x86_64 MOVRS insns + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*66 42 0f 38 8b 94 f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%dx +\s*[a-f0-9]+:\s*66 41 0f 38 8b 11\s+movrs \(%r9\),%dx +\s*[a-f0-9]+:\s*66 0f 38 8b 91 fe 00 00 00\s+movrs 0xfe\(%rcx\),%dx +\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrs -0x100\(%rdx\),%dx +\s*[a-f0-9]+:\s*42 0f 38 8b 94 f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%edx +\s*[a-f0-9]+:\s*41 0f 38 8b 11\s+movrs \(%r9\),%edx +\s*[a-f0-9]+:\s*0f 38 8b 91 fc 01 00 00\s+movrs 0x1fc\(%rcx\),%edx +\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrs -0x200\(%rdx\),%edx +\s*[a-f0-9]+:\s*4e 0f 38 8b a4 f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%r12 +\s*[a-f0-9]+:\s*4d 0f 38 8b 21\s+movrs \(%r9\),%r12 +\s*[a-f0-9]+:\s*4c 0f 38 8b a1 f8 03 00 00\s+movrs 0x3f8\(%rcx\),%r12 +\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrs -0x400\(%rdx\),%r12 +\s*[a-f0-9]+:\s*42 0f 38 8a 9c f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%bl +\s*[a-f0-9]+:\s*41 0f 38 8a 19\s+movrs \(%r9\),%bl +\s*[a-f0-9]+:\s*0f 38 8a 59 7f\s+movrs 0x7f\(%rcx\),%bl +\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrs -0x80\(%rdx\),%bl +\s*[a-f0-9]+:\s*42 0f 18 a4 f5 00 00 00 10\s+prefetchrst2 0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*41 0f 18 21\s+prefetchrst2 \(%r9\) +\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 0x7f\(%rcx\) +\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 -0x80\(%rdx\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-movrs.s b/gas/testsuite/gas/i386/x86-64-movrs.s new file mode 100644 index 00000000000..e15269a8a3e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-movrs.s @@ -0,0 +1,47 @@ +# Check 64bit MOVRS instructions + + .text +_start: + movrs 0x10000000(%rbp, %r14, 8), %dx + movrs (%r9), %dx + movrs 254(%rcx), %dx + movrs -256(%rdx), %dx + movrs 0x10000000(%rbp, %r14, 8), %edx + movrs (%r9), %edx + movrs 508(%rcx), %edx + movrs -512(%rdx), %edx + movrs 0x10000000(%rbp, %r14, 8), %r12 + movrs (%r9), %r12 + movrs 1016(%rcx), %r12 + movrs -1024(%rdx), %r12 + movrs 0x10000000(%rbp, %r14, 8), %bl + movrs (%r9), %bl + movrs 127(%rcx), %bl + movrs -128(%rdx), %bl + prefetchrst2 0x10000000(%rbp, %r14, 8) + prefetchrst2 (%r9) + prefetchrst2 127(%rcx) + prefetchrst2 -128(%rdx) + +_intel: + .intel_syntax noprefix + movrs dx, WORD PTR [rbp+r14*8+0x10000000] + movrs dx, WORD PTR [r9] + movrs dx, WORD PTR [rcx+254] + movrs dx, WORD PTR [rdx-256] + movrs edx, DWORD PTR [rbp+r14*8+0x10000000] + movrs edx, DWORD PTR [r9] + movrs edx, DWORD PTR [rcx+508] + movrs edx, DWORD PTR [rdx-512] + movrs r12, QWORD PTR [rbp+r14*8+0x10000000] + movrs r12, QWORD PTR [r9] + movrs r12, QWORD PTR [rcx+1016] + movrs r12, QWORD PTR [rdx-1024] + movrs bl, BYTE PTR [rbp+r14*8+0x10000000] + movrs bl, BYTE PTR [r9] + movrs bl, BYTE PTR [rcx+127] + movrs bl, BYTE PTR [rdx-128] + prefetchrst2 BYTE PTR [rbp+r14*8+0x10000000] + prefetchrst2 BYTE PTR [r9] + prefetchrst2 BYTE PTR [rcx+127] + prefetchrst2 BYTE PTR [rdx-128] diff --git a/gas/testsuite/gas/i386/x86-64-prefetch-intel.d b/gas/testsuite/gas/i386/x86-64-prefetch-intel.d index b0f9556f942..29c5253019c 100644 --- a/gas/testsuite/gas/i386/x86-64-prefetch-intel.d +++ b/gas/testsuite/gas/i386/x86-64-prefetch-intel.d @@ -22,7 +22,7 @@ Disassembly of section .text: \s*[a-f0-9]+: 0f 18 08 prefetcht0 BYTE PTR \[rax\] \s*[a-f0-9]+: 0f 18 10 prefetcht1 BYTE PTR \[rax\] \s*[a-f0-9]+: 0f 18 18 prefetcht2 BYTE PTR \[rax\] -\s*[a-f0-9]+: 0f 18 20 nop DWORD PTR \[rax\] +\s*[a-f0-9]+: 0f 18 20 prefetchrst2 BYTE PTR \[rax\] \s*[a-f0-9]+: 0f 18 28 nop DWORD PTR \[rax\] \s*[a-f0-9]+: 0f 18 30 nop DWORD PTR \[rax\] \s*[a-f0-9]+: 0f 18 38 nop DWORD PTR \[rax\] diff --git a/gas/testsuite/gas/i386/x86-64-prefetch.d b/gas/testsuite/gas/i386/x86-64-prefetch.d index 3e83ef5bf4c..18205c28188 100644 --- a/gas/testsuite/gas/i386/x86-64-prefetch.d +++ b/gas/testsuite/gas/i386/x86-64-prefetch.d @@ -22,7 +22,7 @@ Disassembly of section .text: \s*[a-f0-9]+: 0f 18 08 prefetcht0 \(%rax\) \s*[a-f0-9]+: 0f 18 10 prefetcht1 \(%rax\) \s*[a-f0-9]+: 0f 18 18 prefetcht2 \(%rax\) -\s*[a-f0-9]+: 0f 18 20 nopl \(%rax\) +\s*[a-f0-9]+: 0f 18 20 prefetchrst2 \(%rax\) \s*[a-f0-9]+: 0f 18 28 nopl \(%rax\) \s*[a-f0-9]+: 0f 18 30 nopl \(%rax\) \s*[a-f0-9]+: 0f 18 38 nopl \(%rax\) diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 645e22e05d8..592e87e2960 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -535,6 +535,12 @@ run_dump_test "x86-64-amx-fp8" run_dump_test "x86-64-amx-fp8-intel" run_list_test "x86-64-amx-fp8-inval" run_dump_test "x86-64-amx-fp8-bad" +run_dump_test "x86-64-movrs" +run_dump_test "x86-64-movrs-intel" +run_dump_test "x86-64-movrs-avx10_2-512" +run_dump_test "x86-64-movrs-avx10_2-512-intel" +run_dump_test "x86-64-movrs-avx10_2-256" +run_dump_test "x86-64-movrs-avx10_2-256-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h index 3a1e0f9b0ea..6a51fb424ea 100644 --- a/opcodes/i386-dis-evex-mod.h +++ b/opcodes/i386-dis-evex-mod.h @@ -8,6 +8,14 @@ { "movbeS", { Mv, Gv }, PREFIX_NP_OR_DATA }, { "%NEmovbeS", { Ev, Gv }, PREFIX_NP_OR_DATA }, }, + /* MOD_EVEX_MAP4_8A_W_0 */ + { + { "movrsB", { Gb, Mb }, NO_PREFIX }, + }, + /* MOD_EVEX_MAP4_8B */ + { + { "movrsS", { Gv, Mv }, PREFIX_NP_OR_DATA }, + }, /* MOD_EVEX_MAP4_F8_P_1 */ { { "enqcmds", { Gva, M }, 0 }, @@ -18,3 +26,7 @@ { "enqcmd", { Gva, M }, 0 }, { VEX_W_TABLE (EVEX_W_MAP4_F8_P3_M_1) }, }, + /* MOD_EVEX_MAP5_6F */ + { + { X86_64_TABLE (X86_64_EVEX_MAP5_6F_M_0) }, + }, diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h index 16fb2698390..f4c65b3c06d 100644 --- a/opcodes/i386-dis-evex-prefix.h +++ b/opcodes/i386-dis-evex-prefix.h @@ -580,6 +580,13 @@ { VEX_W_TABLE (EVEX_W_MAP5_6E_P_1) }, { "vmovwY", { XMScalar, Edw }, 0 }, }, + /* PREFIX_EVEX_MAP5_6F_M_0_X86_64 */ + { + { Bad_Opcode }, + { "vmovrs%DQ", { XM, EXEvexXNoBcst }, 0 }, + { Bad_Opcode }, + { "vmovrs%BW", { XM, EXEvexXNoBcst }, 0 }, + }, /* PREFIX_EVEX_MAP5_74 */ { { "vcvtbiasp%XH2bf8s", { XMxmmq, Vex, EXxh }, 0 }, diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h index 1bb716c0ba7..c183d5516f3 100644 --- a/opcodes/i386-dis-evex-w.h +++ b/opcodes/i386-dis-evex-w.h @@ -452,6 +452,10 @@ { Bad_Opcode }, { "vpshrdw", { XM, Vex, EXx, Ib }, 0 }, }, + /* EVEX_W_MAP4_8A */ + { + { MOD_TABLE (MOD_EVEX_MAP4_8A_W_0) }, + }, /* EVEX_W_MAP4_8F_R_0 */ { { "pop2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX }, diff --git a/opcodes/i386-dis-evex-x86-64.h b/opcodes/i386-dis-evex-x86-64.h new file mode 100644 index 00000000000..b1c8e2a3c7d --- /dev/null +++ b/opcodes/i386-dis-evex-x86-64.h @@ -0,0 +1,5 @@ + /* X86_64_EVEX_MAP5_6F_M_0 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_6F_M_0_X86_64) }, + }, diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 006d0c4a990..5fb06689d2c 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -1030,8 +1030,8 @@ static const struct dis386 evex_table[][256] = { /* 88 */ { "%NFpopcntS", { Gv, Ev }, PREFIX_NP_OR_DATA }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { VEX_W_TABLE (EVEX_W_MAP4_8A) }, + { MOD_TABLE (MOD_EVEX_MAP4_8B) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1290,7 +1290,7 @@ static const struct dis386 evex_table[][256] = { { PREFIX_TABLE (PREFIX_EVEX_MAP5_6C) }, { PREFIX_TABLE (PREFIX_EVEX_MAP5_6D) }, { EVEX_LEN_TABLE (EVEX_LEN_MAP5_6E) }, - { Bad_Opcode }, + { MOD_TABLE (MOD_EVEX_MAP5_6F) }, /* 70 */ { Bad_Opcode }, { Bad_Opcode }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index b1d4b757670..4c140340cd8 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -942,6 +942,7 @@ enum MOD_0F18_REG_1, MOD_0F18_REG_2, MOD_0F18_REG_3, + MOD_0F18_REG_4, MOD_0F18_REG_6, MOD_0F18_REG_7, MOD_0F1A_PREFIX_0, @@ -959,6 +960,8 @@ enum MOD_0FAE_REG_7, MOD_0FC7_REG_6, MOD_0FC7_REG_7, + MOD_0F388A, + MOD_0F388B, MOD_0F38DC_PREFIX_1, MOD_0F38F8, @@ -968,8 +971,12 @@ enum MOD_EVEX_MAP4_60, MOD_EVEX_MAP4_61, + MOD_EVEX_MAP4_8A_W_0, + MOD_EVEX_MAP4_8B, MOD_EVEX_MAP4_F8_P_1, MOD_EVEX_MAP4_F8_P_3, + + MOD_EVEX_MAP5_6F, }; enum @@ -1258,6 +1265,7 @@ enum PREFIX_EVEX_MAP5_6C, PREFIX_EVEX_MAP5_6D, PREFIX_EVEX_MAP5_6E_L_0, + PREFIX_EVEX_MAP5_6F_M_0_X86_64, PREFIX_EVEX_MAP5_74, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, @@ -1346,6 +1354,8 @@ enum X86_64_0F18_REG_7_MOD_0, X86_64_0F24, X86_64_0F26, + X86_64_0F388A_M_0, + X86_64_0F388B_M_0, X86_64_0F38F8_M_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1, @@ -1364,6 +1374,8 @@ enum X86_64_VEX_MAP5_FD, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, X86_64_VEX_MAP7_F8_L_0_W_0_R_0, + + X86_64_EVEX_MAP5_6F_M_0, }; enum @@ -1807,6 +1819,7 @@ enum EVEX_W_0F3A70, EVEX_W_0F3A72, + EVEX_W_MAP4_8A, EVEX_W_MAP4_8F_R_0, EVEX_W_MAP4_F8_P1_M_1, EVEX_W_MAP4_F8_P3_M_1, @@ -2865,7 +2878,7 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F18_REG_1) }, { MOD_TABLE (MOD_0F18_REG_2) }, { MOD_TABLE (MOD_0F18_REG_3) }, - { "nopQ", { Ev }, 0 }, + { MOD_TABLE (MOD_0F18_REG_4) }, { "nopQ", { Ev }, 0 }, { MOD_TABLE (MOD_0F18_REG_6) }, { MOD_TABLE (MOD_0F18_REG_7) }, @@ -4615,6 +4628,18 @@ static const struct dis386 x86_64_table[][2] = { { "movZ", { Td, Em }, 0 }, }, + { + /* X86_64_0F388A_M_0 */ + { Bad_Opcode }, + { "movrsB", { Gb, Mb }, PREFIX_OPCODE }, + }, + + { + /* X86_64_0F388B_M_0 */ + { Bad_Opcode }, + { "movrsS", { Gv, Mv }, PREFIX_OPCODE }, + }, + { /* X86_64_0F38F8_M_1 */ { Bad_Opcode }, @@ -4710,6 +4735,8 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, }, + +#include "i386-dis-evex-x86-64.h" }; static const struct dis386 three_byte_table[][256] = { @@ -4872,8 +4899,8 @@ static const struct dis386 three_byte_table[][256] = { /* 88 */ { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { MOD_TABLE (MOD_0F388A) }, + { MOD_TABLE (MOD_0F388B) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8392,6 +8419,11 @@ static const struct dis386 mod_table[][2] = { { "prefetcht2", { Mb }, 0 }, { "nopQ", { Ev }, 0 }, }, + { + /* MOD_0F18_REG_4 */ + { "prefetchrst2", { Mb }, 0 }, + { "nopQ", { Ev }, 0 }, + }, { /* MOD_0F18_REG_6 */ { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) }, @@ -8477,6 +8509,14 @@ static const struct dis386 mod_table[][2] = { { "vmptrst", { Mq }, 0 }, { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } }, + { + /* MOD_0F388A */ + { X86_64_TABLE (X86_64_0F388A_M_0) }, + }, + { + /* MOD_0F388B */ + { X86_64_TABLE (X86_64_0F388B_M_0) }, + }, { /* MOD_0F38DC_PREFIX_1 */ { "aesenc128kl", { XM, M }, 0 }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 40a744eba41..9824d7a0bd1 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -417,6 +417,7 @@ static bitfield cpu_flags[] = BITFIELD (MSR_IMM), BITFIELD (APX_F), BITFIELD (AVX10_2), + BITFIELD (MOVRS), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 55260d30d3e..32d5955e680 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -229,6 +229,8 @@ enum i386_cpu CpuUSER_MSR, /* Intel MSR_IMM Instructions support required. */ CpuMSR_IMM, + /* Intel MOVRS Instructions support required. */ + CpuMOVRS, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -493,6 +495,7 @@ typedef union i386_cpu_flags unsigned int cpulkgs:1; unsigned int cpuuser_msr:1; unsigned int cpumsr_imm:1; + unsigned int cpumovrs:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 246e9a837c2..2f7d6de6888 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3554,3 +3554,17 @@ vcomxs, 0x2f, AVX10_2, Modrm|EVexLIG|||Disp8M vucomxs, 0x2e, AVX10_2, Modrm|EVexLIG|||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM } // AVX10.2 instructions end. + +// MOVRS instructions. + +prefetchrst2, 0xf18/4, MOVRS, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } + +movrs, 0x8a, MOVRS&x64, Modrm|Space0F38|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Byte|Unspecified|BaseIndex, Reg8 } +movrs, 0x8b, MOVRS&x64, Modrm|Anysize|Space0F38|CheckOperandSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movrs, 0x8a, MOVRS&APX_F, Modrm|EVex128|EVexMap4|VexW0|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Byte|Unspecified|BaseIndex, Reg8 } +movrs, 0x8b, MOVRS&APX_F, Modrm|CheckOperandSize|EVex128|EVexMap4|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + +vmovrs, 0xf26f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5||Disp8ShiftVL|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovrs, 0xf36f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5||Disp8ShiftVL|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +// MOVRS instructions end. From patchwork Tue Dec 24 09:24:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haochen Jiang X-Patchwork-Id: 103666 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0C1E13858CDA for ; Tue, 24 Dec 2024 09:30:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0C1E13858CDA Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Ia/xeNKc X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by sourceware.org (Postfix) with ESMTPS id 302F33858428 for ; Tue, 24 Dec 2024 09:25:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 302F33858428 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 302F33858428 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1735032301; cv=none; b=lBVG0nsIdgICB1mwKL5kM+byYxMLZAaFpBWz0BKYWVrJM15+uStCakYGocwF7S8YkPWfbWfPZDu6rJwVre776/X6QEgqMKfOiFw+/BZgPabNrbPyEEo3dBaISewHjbspHDoX7RqT98bl8hinYsYY/vevZ3ye9dnUwROiFa3mykU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1735032301; c=relaxed/simple; bh=l5b4HP3M3y6B6NEs0LAeEZnX1eKSVnAEboEOcAseE4g=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=xrdAY+QiDAxJqfA2pufJs5XpWtL52fwuEhyfanyeZiz7+EWzUxcUwjI/PYNxxaOQAvpxY58TvvTZ/knCX9Ym3iR1s5NSL1C954gbETQqdoV88z3cuWun2bH+EUWZFkLyu+Wok2TEH3TGe5OE/jhul47YDq1b2no2uPpgdtfWrMQ= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 302F33858428 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1735032301; x=1766568301; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l5b4HP3M3y6B6NEs0LAeEZnX1eKSVnAEboEOcAseE4g=; b=Ia/xeNKcaUOV8gIUKD7C3mUL6wVy9l1KFdYCNU5uH9AYoX5LZuYRyxUO bvxC9DkBBcWW9GVCcA/BmfaQ00/K9+GExEMY8x43oyqcIsvCDfNGPzt7L QsAOl8mD9VNAWc7t4bGSGJigXglYsmuruYXzsFzYRJDqmBnoSzoJHFxZH 5IvnW5345Ng6NCzDdJlaEnqNKxNrZFBZ/AhBxttJhmbZBRV+8oUY+zxIl kmP4bjMrHtgOH6RZyq1poMu0JQW/bgm9ZZHog4gNbAQNQRz4rX3DP0R2b rr2y2RJDQpc5gNox0ii881yDpyYhOIz1YbpFNvECQpktKkWGGGX2pCT/5 Q==; X-CSE-ConnectionGUID: 8nrW++ZIT2KM8HbTMyipzQ== X-CSE-MsgGUID: a89a8gqEQr2J2wdM71fsQQ== X-IronPort-AV: E=McAfee;i="6700,10204,11295"; a="39180933" X-IronPort-AV: E=Sophos;i="6.12,259,1728975600"; d="scan'208";a="39180933" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Dec 2024 01:25:01 -0800 X-CSE-ConnectionGUID: +eOWvfNSQ4q+bYnuL4RFwg== X-CSE-MsgGUID: uDeNGovcTJe5IwqbYNTYyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,259,1728975600"; d="scan'208";a="99526343" Received: from shliclel4217.sh.intel.com ([10.239.240.127]) by orviesa006.jf.intel.com with ESMTP; 24 Dec 2024 01:24:59 -0800 From: Haochen Jiang To: binutils@sourceware.org Cc: hjl.tools@gmail.com, jbeulich@suse.com, "Hu, Lin1" Subject: [PATCH v2 2/2] Support Intel AMX-MOVRS Date: Tue, 24 Dec 2024 17:24:52 +0800 Message-Id: <20241224092452.1825164-3-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20241224092452.1825164-1-haochen.jiang@intel.com> References: <20241224092452.1825164-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: "Hu, Lin1" Changes in v2: - Add APX_F extension for AMX-MOVRS. - Add invalid testcase for sibmem. - Templatize the table for T2RPNTLVW[Z0,Z1]RS[,T1]. --- This patch will support AMX-MOVRS feature. Unlike all the other AMX insns in vector space where we pass vex_len_table before vex_w_table, we first pass vex_w_table for tileloaddrs[,t1] to align with the order in EVEX space. The reason why we first pass vex_w_table in EVEX space is due to AMX-AVX512, where tcvtrowd2ps and tilemovrow with r32 shares the same opcode with tileloaddrs[,t1]. All of them have evex.w = 0 but with different evex.length. Re-doing that shortly is not ideal. APX_F extension is also implemented in this patch. The encoding will be: - EVEX.128.NP/66.MAP5.W0 F8/F9 !(11):rrr:100 for T2RPNTLVW[Z0,Z1]RS[,T1] with NF=0. - EVEX.128.F2/66.0F38.W0 4A !(11):rrr:100 FOR TILELOADDRS[,T1] with NF=0. --- gas/ChangeLog: * NEWS: Support Intel AMX-MOVRS. * config/tc-i386.c: Add amx_movrs. * doc/c-i386.texi: Document .amx_movrs. * testsuite/gas/i386/x86-64.exp: Run AMX-MOVRS tests. * testsuite/gas/i386/x86-64-amx-movrs-intel.d: New test. * testsuite/gas/i386/x86-64-amx-movrs-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-movrs-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.d: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-len.h (EVEX_LEN_0F384A_X86_64_W_0): New. * i386-dis-evex-w.h (EVEX_W_0F384A_X86_64): Ditto. * i386-dis-evex-x86-64.h (X86_64_EVEX_0F384A): Ditto. * i386-dis-evex.h: New entry for AMX-MOVRS. * i386-dis.c: (MOD_VEX_MAP5_F8_X86_64): Ditto. (MOD_VEX_MAP5_F9_X86_64): Ditto. (PREFIX_VEX_0F384A_X86_64_M_0_L_0_W_0): Ditto. (PREFIX_VEX_MAP5_F8_X86_64_M_0_L_0_W_0): Ditto. (PREFIX_VEX_MAP5_F9_X86_64_M_0_L_0_W_0): Ditto. (X86_64_VEX_0F384A): Ditto. (X86_64_VEX_MAP5_F8): Ditto. (X86_64_VEX_MAP5_F9): Ditto. (X86_64_EVEX_0F384A): Ditto. (VEX_LEN_0F384A_X86_64_W_0): Ditto. (VEX_LEN_MAP5_F8_X86_64_M_0): Ditto. (VEX_LEN_MAP5_F9_X86_64_M_0): Ditto. (EVEX_LEN_0F384A_X86_64_W_0): Ditto. (VEX_W_0F384A_X86_64): Ditto. (VEX_W_MAP5_F8_X86_64): Ditto. (VEX_W_MAP5_F9_X86_64): Ditto. (EVEX_W_0F384A_X86_64): Ditto. (prefix_table): New entry for AMX-MOVRS. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map5_f8_opcode): New. (map5_f9_opcode): Ditto. (get_valid_dis386): Handle VEX_MAP5 opcode for AMX-MOVRS. * i386-gen.c (isa_dependencies): Add AMX_MOVRS. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_MOVRS): New. (i386_cpu_flags): Add cpuamx_movrs. * i386-opc.tbl: Add AMX-MOVRS instructions. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 7 +- gas/doc/c-i386.texi | 3 +- .../gas/i386/x86-64-amx-movrs-intel.d | 23 + .../gas/i386/x86-64-amx-movrs-inval.l | 13 + .../gas/i386/x86-64-amx-movrs-inval.s | 19 + gas/testsuite/gas/i386/x86-64-amx-movrs.d | 21 + gas/testsuite/gas/i386/x86-64-amx-movrs.s | 31 + .../gas/i386/x86-64-apx-evex-promoted-intel.d | 16 + .../gas/i386/x86-64-apx-evex-promoted-wig.d | 16 + .../gas/i386/x86-64-apx-evex-promoted.d | 16 + .../gas/i386/x86-64-apx-evex-promoted.s | 16 + gas/testsuite/gas/i386/x86-64.exp | 3 + opcodes/i386-dis-evex-len.h | 5 + opcodes/i386-dis-evex-w.h | 4 + opcodes/i386-dis-evex-x86-64.h | 5 + opcodes/i386-dis-evex.h | 6 +- opcodes/i386-dis.c | 106 +- opcodes/i386-gen.c | 3 + opcodes/i386-init.h | 690 +-- opcodes/i386-mnem.h | 4362 +++++++++-------- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 6 + opcodes/i386-tbl.h | 369 +- 23 files changed, 3091 insertions(+), 2652 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-amx-movrs-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-amx-movrs-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-amx-movrs-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-amx-movrs.d create mode 100644 gas/testsuite/gas/i386/x86-64-amx-movrs.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 31c367aadbc..7b05d4e5c0b 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1185,6 +1185,7 @@ static const arch_entry cpu_arch[] = SUBARCH (amx_transpose, AMX_TRANSPOSE, ANY_AMX_TRANSPOSE, false), SUBARCH (amx_tf32, AMX_TF32, ANY_AMX_TF32, false), SUBARCH (amx_fp8, AMX_FP8, ANY_AMX_FP8, false), + SUBARCH (amx_movrs, AMX_MOVRS, ANY_AMX_MOVRS, false), SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false), SUBARCH (movdiri, MOVDIRI, MOVDIRI, false), SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false), @@ -2250,7 +2251,8 @@ cpu_flags_match (const insn_template *t) || any.bitfield.cpuavx512f || any.bitfield.cpuavx512bw || any.bitfield.cpuavx512dq || any.bitfield.cpuamx_tile || any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr - || any.bitfield.cpumsr_imm || any.bitfield.cpuamx_transpose)) + || any.bitfield.cpumsr_imm || any.bitfield.cpuamx_transpose + || any.bitfield.cpuamx_movrs)) { /* These checks (verifying that APX_F() was properly used in the opcode table entry) make sure there's no need for an "else" to @@ -4055,7 +4057,8 @@ install_template (const insn_template *t) || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ) || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI) || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR) - || maybe_cpu (t, CpuMSR_IMM) || maybe_cpu (t, CpuAMX_TRANSPOSE)) + || maybe_cpu (t, CpuMSR_IMM) || maybe_cpu (t, CpuAMX_TRANSPOSE) + || maybe_cpu (t, CpuAMX_MOVRS)) && maybe_cpu (t, CpuAPX_F)) { if (need_evex_encoding (t)) diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 47d5ec66140..d07fb817fe4 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -232,6 +232,7 @@ accept various extension mnemonics. For example, @code{amx_transpose}, @code{amx_tf32}, @code{amx_fp8} +@code{amx_movrs}, @code{amx_tile}, @code{vmx}, @code{vmfunc}, @@ -1706,7 +1707,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16} @item @samp{.amx_complex} @tab @samp{.amx_transpose} @tab @samp{.amx_tf32} -@item @samp{.amx_fp8} @tab @samp{.amx_tile} +@item @samp{.amx_fp8} @tab @samp{.amx_movrs} @tab @samp{.amx_tile} @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} diff --git a/gas/testsuite/gas/i386/x86-64-amx-movrs-intel.d b/gas/testsuite/gas/i386/x86-64-amx-movrs-intel.d new file mode 100644 index 00000000000..f4cd0bd0911 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-amx-movrs-intel.d @@ -0,0 +1,23 @@ +#objdump: -dw -Mintel +#name: x86_64 AMX-MOVRS insns (Intel disassembly) +#source: x86-64-amx-movrs.s + +.*: +file format .* + +Disassembly of section \.text: + +#... +[a-f0-9]+ <_intel>: +\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs tmm6,\[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs tmm2,\[r9\+riz\*1\] +\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 tmm6,\[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 tmm2,\[r9\+riz\*1\] +\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs tmm6,\[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs tmm2,\[r9\+riz\*1\] +\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 tmm6,\[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 tmm2,\[r9\+riz\*1\] +\s*[a-f0-9]+:\s*c4 a2 7b 4a b4 f5 00 00 00 10\s+tileloaddrs tmm6,\[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 c2 7b 4a 1c 21\s+tileloaddrs tmm3,\[r9\+riz\*1\] +\s*[a-f0-9]+:\s*c4 a2 79 4a b4 f5 00 00 00 10\s+tileloaddrst1 tmm6,\[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 c2 79 4a 1c 21\s+tileloaddrst1 tmm3,\[r9\+riz\*1\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-amx-movrs-inval.l b/gas/testsuite/gas/i386/x86-64-amx-movrs-inval.l new file mode 100644 index 00000000000..aa49c0d3533 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-amx-movrs-inval.l @@ -0,0 +1,13 @@ +.* Assembler messages: +.*:5: Error: `\(%rip\)' cannot be used here +.*:6: Error: `\(%rip\)' cannot be used here +.*:7: Error: `\(%rip\)' cannot be used here +.*:8: Error: `\(%rip\)' cannot be used here +.*:9: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0rs' +.*:10: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0rst1' +.*:11: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1rs' +.*:12: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1rst1' +.*:16: Error: `t2rpntlvwz0rs' is not supported on `x86_64.noamx_transpose' +.*:17: Error: `t2rpntlvwz0rst1' is not supported on `x86_64.noamx_transpose' +.*:18: Error: `t2rpntlvwz1rs' is not supported on `x86_64.noamx_transpose' +.*:19: Error: `t2rpntlvwz1rst1' is not supported on `x86_64.noamx_transpose' diff --git a/gas/testsuite/gas/i386/x86-64-amx-movrs-inval.s b/gas/testsuite/gas/i386/x86-64-amx-movrs-inval.s new file mode 100644 index 00000000000..98b54f38ece --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-amx-movrs-inval.s @@ -0,0 +1,19 @@ +# Check Invalid 64bit AMX-MOVRS instructions + + .text +_start: + t2rpntlvwz0rs (%rip), %tmm2 + t2rpntlvwz0rst1 (%rip), %tmm2 + t2rpntlvwz1rs (%rip), %tmm2 + t2rpntlvwz1rst1 (%rip), %tmm2 + t2rpntlvwz0rs (%r9), %tmm1 + t2rpntlvwz0rst1 (%r9), %tmm3 + t2rpntlvwz1rs (%r9), %tmm5 + t2rpntlvwz1rst1 (%r9), %tmm7 + + .arch .noamx_transpose +_transpose: + t2rpntlvwz0rs (%r9), %tmm2 + t2rpntlvwz0rst1 (%r9), %tmm2 + t2rpntlvwz1rs (%r9), %tmm2 + t2rpntlvwz1rst1 (%r9), %tmm2 diff --git a/gas/testsuite/gas/i386/x86-64-amx-movrs.d b/gas/testsuite/gas/i386/x86-64-amx-movrs.d new file mode 100644 index 00000000000..b0bc77e8f15 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-amx-movrs.d @@ -0,0 +1,21 @@ +#objdump: -dw +#name: x86_64 AMX-MOVRS insns + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs 0x10000000\(%rbp,%r14,8\),%tmm6 +\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs \(%r9,%riz,1\),%tmm2 +\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 0x10000000\(%rbp,%r14,8\),%tmm6 +\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 \(%r9,%riz,1\),%tmm2 +\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs 0x10000000\(%rbp,%r14,8\),%tmm6 +\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs \(%r9,%riz,1\),%tmm2 +\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 0x10000000\(%rbp,%r14,8\),%tmm6 +\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 \(%r9,%riz,1\),%tmm2 +\s*[a-f0-9]+:\s*c4 a2 7b 4a b4 f5 00 00 00 10\s+tileloaddrs 0x10000000\(%rbp,%r14,8\),%tmm6 +\s*[a-f0-9]+:\s*c4 c2 7b 4a 1c 21\s+tileloaddrs \(%r9,%riz,1\),%tmm3 +\s*[a-f0-9]+:\s*c4 a2 79 4a b4 f5 00 00 00 10\s+tileloaddrst1 0x10000000\(%rbp,%r14,8\),%tmm6 +\s*[a-f0-9]+:\s*c4 c2 79 4a 1c 21\s+tileloaddrst1 \(%r9,%riz,1\),%tmm3 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-amx-movrs.s b/gas/testsuite/gas/i386/x86-64-amx-movrs.s new file mode 100644 index 00000000000..07b6aba2a57 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-amx-movrs.s @@ -0,0 +1,31 @@ +# Check 64bit AMX-MOVRS instructions + + .text +_start: + t2rpntlvwz0rs 0x10000000(%rbp, %r14, 8), %tmm6 + t2rpntlvwz0rs (%r9), %tmm2 + t2rpntlvwz0rst1 0x10000000(%rbp, %r14, 8), %tmm6 + t2rpntlvwz0rst1 (%r9), %tmm2 + t2rpntlvwz1rs 0x10000000(%rbp, %r14, 8), %tmm6 + t2rpntlvwz1rs (%r9), %tmm2 + t2rpntlvwz1rst1 0x10000000(%rbp, %r14, 8), %tmm6 + t2rpntlvwz1rst1 (%r9), %tmm2 + tileloaddrs 0x10000000(%rbp, %r14, 8), %tmm6 + tileloaddrs (%r9), %tmm3 + tileloaddrst1 0x10000000(%rbp, %r14, 8), %tmm6 + tileloaddrst1 (%r9), %tmm3 + +_intel: + .intel_syntax noprefix + t2rpntlvwz0rs tmm6, [rbp+r14*8+0x10000000] + t2rpntlvwz0rs tmm2, [r9] + t2rpntlvwz0rst1 tmm6, [rbp+r14*8+0x10000000] + t2rpntlvwz0rst1 tmm2, [r9] + t2rpntlvwz1rs tmm6, [rbp+r14*8+0x10000000] + t2rpntlvwz1rs tmm2, [r9] + t2rpntlvwz1rst1 tmm6, [rbp+r14*8+0x10000000] + t2rpntlvwz1rst1 tmm2, [r9] + tileloaddrs tmm6, [rbp+r14*8+0x10000000] + tileloaddrs tmm3, [r9] + tileloaddrst1 tmm6, [rbp+r14*8+0x10000000] + tileloaddrst1 tmm3, [r9] diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d index a45711c5b4b..ab03bdb0409 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d @@ -141,11 +141,19 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+\[r31\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7d 08 4b b4 87 23 01 00 00[ ]+tileloaddt1 tmm6,\[r31\+rax\*4\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+tmm6,\[rbp\+r31\*8\+0x10000000\] +[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+tmm3,\[r16\+riz\*1\] +[ ]*[a-f0-9]+:[ ]*62 9a 7d 08 4a b4 f7 00 00 00 10[ ]+tileloaddrst1[ ]+tmm6,\[r31\+r14\*8\+0x10000000\] +[ ]*[a-f0-9]+:[ ]*62 fa 7d 08 4a 1c 20[ ]+tileloaddrst1[ ]+tmm3,\[r16\+riz\*1\] [ ]*[a-f0-9]+:[ ]*62 da 7e 08 4b b4 87 23 01 00 00[ ]+tilestored[ ]+\[r31\+rax\*4\+0x123\],tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\] [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 66 8c 87 23 01 00 00[ ]+wrssd[ ]+\[r31\+rax\*4\+0x123\],r25d [ ]*[a-f0-9]+:[ ]*62 4c fc 08 66 bc 87 23 01 00 00[ ]+wrssq[ ]+\[r31\+rax\*4\+0x123\],r31 [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 65 8c 87 23 01 00 00[ ]+wrussd[ ]+\[r31\+rax\*4\+0x123\],r25d @@ -280,11 +288,19 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+\[r31\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7d 08 4b b4 87 23 01 00 00[ ]+tileloaddt1 tmm6,\[r31\+rax\*4\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+tmm6,\[rbp\+r31\*8\+0x10000000\] +[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+tmm3,\[r16\+riz\*1\] +[ ]*[a-f0-9]+:[ ]*62 9a 7d 08 4a b4 f7 00 00 00 10[ ]+tileloaddrst1[ ]+tmm6,\[r31\+r14\*8\+0x10000000\] +[ ]*[a-f0-9]+:[ ]*62 fa 7d 08 4a 1c 20[ ]+tileloaddrst1[ ]+tmm3,\[r16\+riz\*1\] [ ]*[a-f0-9]+:[ ]*62 da 7e 08 4b b4 87 23 01 00 00[ ]+tilestored[ ]+\[r31\+rax\*4\+0x123\],tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\] [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 66 8c 87 23 01 00 00[ ]+wrssd[ ]+\[r31\+rax\*4\+0x123\],r25d [ ]*[a-f0-9]+:[ ]*62 4c fc 08 66 bc 87 23 01 00 00[ ]+wrssq[ ]+\[r31\+rax\*4\+0x123\],r31 [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 65 8c 87 23 01 00 00[ ]+wrussd[ ]+\[r31\+rax\*4\+0x123\],r25d diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d index 50a406cbfa6..7eac242c96b 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d @@ -141,11 +141,19 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 4b b4 87 23 01 00 00[ ]+tileloaddt1[ ]+0x123\(%r31,%rax,4\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3 +[ ]*[a-f0-9]+:[ ]*62 9a 7d 08 4a b4 f7 00 00 00 10[ ]+tileloaddrst1[ ]+0x10000000\(%r31,%r14,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 fa 7d 08 4a 1c 20[ ]+tileloaddrst1[ ]+\(%r16,%riz,1\),%tmm3 [ ]*[a-f0-9]+:[ ]*62 da 7e 08 4b b4 87 23 01 00 00[ ]+tilestored[ ]+%tmm6,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 66 8c 87 23 01 00 00[ ]+wrssd[ ]+%r25d,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c fc 08 66 bc 87 23 01 00 00[ ]+wrssq[ ]+%r31,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 65 8c 87 23 01 00 00[ ]+wrussd[ ]+%r25d,0x123\(%r31,%rax,4\) @@ -280,11 +288,19 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 4b b4 87 23 01 00 00[ ]+tileloaddt1[ ]+0x123\(%r31,%rax,4\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3 +[ ]*[a-f0-9]+:[ ]*62 9a 7d 08 4a b4 f7 00 00 00 10[ ]+tileloaddrst1[ ]+0x10000000\(%r31,%r14,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 fa 7d 08 4a 1c 20[ ]+tileloaddrst1[ ]+\(%r16,%riz,1\),%tmm3 [ ]*[a-f0-9]+:[ ]*62 da 7e 08 4b b4 87 23 01 00 00[ ]+tilestored[ ]+%tmm6,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 66 8c 87 23 01 00 00[ ]+wrssd[ ]+%r25d,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c fc 08 66 bc 87 23 01 00 00[ ]+wrssq[ ]+%r31,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 65 8c 87 23 01 00 00[ ]+wrussd[ ]+%r25d,0x123\(%r31,%rax,4\) diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d index 3e5938ab019..5dc5efc4197 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d @@ -141,11 +141,19 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 4b b4 87 23 01 00 00[ ]+tileloaddt1[ ]+0x123\(%r31,%rax,4\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3 +[ ]*[a-f0-9]+:[ ]*62 9a 7d 08 4a b4 f7 00 00 00 10[ ]+tileloaddrst1[ ]+0x10000000\(%r31,%r14,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 fa 7d 08 4a 1c 20[ ]+tileloaddrst1[ ]+\(%r16,%riz,1\),%tmm3 [ ]*[a-f0-9]+:[ ]*62 da 7e 08 4b b4 87 23 01 00 00[ ]+tilestored[ ]+%tmm6,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 66 8c 87 23 01 00 00[ ]+wrssd[ ]+%r25d,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c fc 08 66 bc 87 23 01 00 00[ ]+wrssq[ ]+%r31,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 65 8c 87 23 01 00 00[ ]+wrussd[ ]+%r25d,0x123\(%r31,%rax,4\) @@ -280,11 +288,19 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 4b b4 87 23 01 00 00[ ]+tileloaddt1[ ]+0x123\(%r31,%rax,4\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3 +[ ]*[a-f0-9]+:[ ]*62 9a 7d 08 4a b4 f7 00 00 00 10[ ]+tileloaddrst1[ ]+0x10000000\(%r31,%r14,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 fa 7d 08 4a 1c 20[ ]+tileloaddrst1[ ]+\(%r16,%riz,1\),%tmm3 [ ]*[a-f0-9]+:[ ]*62 da 7e 08 4b b4 87 23 01 00 00[ ]+tilestored[ ]+%tmm6,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6 +[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 66 8c 87 23 01 00 00[ ]+wrssd[ ]+%r25d,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c fc 08 66 bc 87 23 01 00 00[ ]+wrssq[ ]+%r31,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 65 8c 87 23 01 00 00[ ]+wrussd[ ]+%r25d,0x123\(%r31,%rax,4\) diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s index bcac9caff7b..689a3e95489 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s @@ -135,11 +135,19 @@ _start: sttilecfg 0x123(%r31,%rax,4) tileloadd 0x123(%r31,%rax,4),%tmm6 tileloaddt1 0x123(%r31,%rax,4),%tmm6 + tileloaddrs 0x10000000(%rbp, %r31, 8), %tmm6 + tileloaddrs (%r16), %tmm3 + tileloaddrst1 0x10000000(%r31, %r14, 8), %tmm6 + tileloaddrst1 (%r16), %tmm3 tilestored %tmm6,0x123(%r31,%rax,4) t2rpntlvwz0 0x123(%r31,%rax,8),%tmm6 t2rpntlvwz0t1 0x123(%r31,%rax,8),%tmm6 t2rpntlvwz1 0x123(%r31,%rax,8),%tmm6 t2rpntlvwz1t1 0x123(%r31,%rax,8),%tmm6 + t2rpntlvwz0rs 0x123(%r31,%rax,8),%tmm6 + t2rpntlvwz0rst1 0x123(%r31,%rax,8),%tmm6 + t2rpntlvwz1rs 0x123(%r31,%rax,8),%tmm6 + t2rpntlvwz1rst1 0x123(%r31,%rax,8),%tmm6 wrssd %r25d,0x123(%r31,%rax,4) wrssq %r31,0x123(%r31,%rax,4) wrussd %r25d,0x123(%r31,%rax,4) @@ -276,11 +284,19 @@ _start: sttilecfg [r31+rax*4+0x123] tileloadd tmm6,[r31+rax*4+0x123] tileloaddt1 tmm6,[r31+rax*4+0x123] + tileloaddrs tmm6, [rbp+r31*8+0x10000000] + tileloaddrs tmm3, [r16] + tileloaddrst1 tmm6, [r31+r14*8+0x10000000] + tileloaddrst1 tmm3, [r16] tilestored [r31+rax*4+0x123],tmm6 t2rpntlvwz0 tmm6,[r31+rax*8+0x123] t2rpntlvwz0t1 tmm6,[r31+rax*8+0x123] t2rpntlvwz1 tmm6,[r31+rax*8+0x123] t2rpntlvwz1t1 tmm6,[r31+rax*8+0x123] + t2rpntlvwz0rs tmm6,[r31+rax*8+0x123] + t2rpntlvwz0rst1 tmm6,[r31+rax*8+0x123] + t2rpntlvwz1rs tmm6,[r31+rax*8+0x123] + t2rpntlvwz1rst1 tmm6,[r31+rax*8+0x123] wrssd DWORD PTR [r31+rax*4+0x123],r25d wrssq QWORD PTR [r31+rax*4+0x123],r31 wrussd DWORD PTR [r31+rax*4+0x123],r25d diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 592e87e2960..d99e0fa43ba 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -535,6 +535,9 @@ run_dump_test "x86-64-amx-fp8" run_dump_test "x86-64-amx-fp8-intel" run_list_test "x86-64-amx-fp8-inval" run_dump_test "x86-64-amx-fp8-bad" +run_dump_test "x86-64-amx-movrs" +run_dump_test "x86-64-amx-movrs-intel" +run_list_test "x86-64-amx-movrs-inval" run_dump_test "x86-64-movrs" run_dump_test "x86-64-movrs-intel" run_dump_test "x86-64-movrs-avx10_2-512" diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h index e931fdd655a..2b4361f7ae6 100644 --- a/opcodes/i386-dis-evex-len.h +++ b/opcodes/i386-dis-evex-len.h @@ -44,6 +44,11 @@ static const struct dis386 evex_len_table[][3] = { { "vperm%DQ", { XM, Vex, EXx }, PREFIX_DATA }, }, + /* EVEX_LEN_0F384A_X86_64_W_0 */ + { + { X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F384A_X86_64_W_0_L_0) }, + }, + /* EVEX_LEN_0F385A */ { { Bad_Opcode }, diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h index c183d5516f3..4ca3664e1ad 100644 --- a/opcodes/i386-dis-evex-w.h +++ b/opcodes/i386-dis-evex-w.h @@ -346,6 +346,10 @@ { { "vpbroadcastmw2dY", { XM, MaskR }, 0 }, }, + /* EVEX_W_0F384A_X86_64 */ + { + { EVEX_LEN_TABLE (EVEX_LEN_0F384A_X86_64_W_0) }, + }, /* EVEX_W_0F3859 */ { { "vbroadcasti32x2", { XM, EXq }, PREFIX_DATA }, diff --git a/opcodes/i386-dis-evex-x86-64.h b/opcodes/i386-dis-evex-x86-64.h index b1c8e2a3c7d..056a479536f 100644 --- a/opcodes/i386-dis-evex-x86-64.h +++ b/opcodes/i386-dis-evex-x86-64.h @@ -1,3 +1,8 @@ + /* X86_64_EVEX_0F384A */ + { + { Bad_Opcode }, + { VEX_W_TABLE (EVEX_W_0F384A_X86_64) }, + }, /* X86_64_EVEX_MAP5_6F_M_0 */ { { Bad_Opcode }, diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 5fb06689d2c..86cef4bd07b 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -376,7 +376,7 @@ static const struct dis386 evex_table[][256] = { /* 48 */ { Bad_Opcode }, { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F3849_X86_64_L_0) }, - { Bad_Opcode }, + { X86_64_TABLE (X86_64_EVEX_0F384A) }, { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F384B_X86_64_L_0) }, { "vrcp14p%XW", { XM, EXx }, PREFIX_DATA }, { "vrcp14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, @@ -1445,8 +1445,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* F8 */ - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_MAP5_F8) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_MAP5_F9) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 4c140340cd8..2adfc2bc567 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -968,6 +968,8 @@ enum MOD_VEX_0F3849_X86_64_L_0_W_0, MOD_VEX_0F386E_X86_64, MOD_VEX_0F386F_X86_64, + MOD_VEX_MAP5_F8_X86_64, + MOD_VEX_MAP5_F9_X86_64, MOD_EVEX_MAP4_60, MOD_EVEX_MAP4_61, @@ -1141,6 +1143,7 @@ enum PREFIX_VEX_0F3848_X86_64_L_0_W_0, PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0, PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1, + PREFIX_VEX_0F384A_X86_64_W_0_L_0, PREFIX_VEX_0F384B_X86_64_L_0_W_0, PREFIX_VEX_0F3850_W_0, PREFIX_VEX_0F3851_W_0, @@ -1166,6 +1169,8 @@ enum PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, PREFIX_VEX_0F3AF0_L_0, + PREFIX_VEX_MAP5_F8_X86_64_M_0_L_0_W_0, + PREFIX_VEX_MAP5_F9_X86_64_M_0_L_0_W_0, PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0, PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, @@ -1361,6 +1366,7 @@ enum X86_64_VEX_0F3848, X86_64_VEX_0F3849, + X86_64_VEX_0F384A, X86_64_VEX_0F384B, X86_64_VEX_0F385C, X86_64_VEX_0F385E, @@ -1371,10 +1377,14 @@ enum X86_64_VEX_0F386F, X86_64_VEX_0F38Ex, + X86_64_VEX_MAP5_F8, + X86_64_VEX_MAP5_F9, X86_64_VEX_MAP5_FD, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, X86_64_VEX_MAP7_F8_L_0_W_0_R_0, + X86_64_EVEX_0F384A, + X86_64_EVEX_MAP5_6F_M_0, }; @@ -1448,6 +1458,7 @@ enum VEX_LEN_0F3841, VEX_LEN_0F3848_X86_64, VEX_LEN_0F3849_X86_64, + VEX_LEN_0F384A_X86_64_W_0, VEX_LEN_0F384B_X86_64, VEX_LEN_0F385A, VEX_LEN_0F385C_X86_64, @@ -1495,6 +1506,8 @@ enum VEX_LEN_0F3ADE_W_0, VEX_LEN_0F3ADF, VEX_LEN_0F3AF0, + VEX_LEN_MAP5_F8_X86_64_M_0, + VEX_LEN_MAP5_F9_X86_64_M_0, VEX_LEN_MAP5_FD_X86_64, VEX_LEN_MAP7_F6, VEX_LEN_MAP7_F8, @@ -1567,6 +1580,7 @@ enum EVEX_LEN_0F381A, EVEX_LEN_0F381B, EVEX_LEN_0F3836, + EVEX_LEN_0F384A_X86_64_W_0, EVEX_LEN_0F385A, EVEX_LEN_0F385B, EVEX_LEN_0F38C6, @@ -1621,6 +1635,7 @@ enum VEX_W_0F3846, VEX_W_0F3848_X86_64_L_0, VEX_W_0F3849_X86_64_L_0, + VEX_W_0F384A_X86_64, VEX_W_0F384B_X86_64_L_0, VEX_W_0F3850, VEX_W_0F3851, @@ -1668,6 +1683,8 @@ enum VEX_W_0F3ACE, VEX_W_0F3ACF, VEX_W_0F3ADE, + VEX_W_MAP5_F8_X86_64_M_0_L_0, + VEX_W_MAP5_F9_X86_64_M_0_L_0, VEX_W_MAP5_FD_X86_64_L_0, VEX_W_MAP7_F6_L_0, VEX_W_MAP7_F8_L_0, @@ -1795,6 +1812,7 @@ enum EVEX_W_0F3835_P_2, EVEX_W_0F3837, EVEX_W_0F383A_P_1, + EVEX_W_0F384A_X86_64, EVEX_W_0F3859, EVEX_W_0F385A_L_n, EVEX_W_0F385B_L_2, @@ -4112,6 +4130,14 @@ static const struct dis386 prefix_table[][4] = { { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) }, }, + /* PREFIX_VEX_0F384A_X86_64_W_0_L_0 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "tileloaddrst1", { TMM, MVexSIBMEM }, 0 }, + { "tileloaddrs", { TMM, MVexSIBMEM }, 0 }, + }, + /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */ { { Bad_Opcode }, @@ -4296,6 +4322,20 @@ static const struct dis386 prefix_table[][4] = { { "%XErorxS", { Gdq, Edq, Ib }, 0 }, }, + /* PREFIX_VEX_MAP5_F8_X86_64_M_0_L_0_W_0 */ + { + { "t2rpntlvwz0rs", { TMM, MVexSIBMEM }, 0 }, + { Bad_Opcode }, + { "t2rpntlvwz1rs", { TMM, MVexSIBMEM }, 0 }, + }, + + /* PREFIX_VEX_MAP5_F9_X86_64_M_0_L_0_W_0 */ + { + { "t2rpntlvwz0rst1", { TMM, MVexSIBMEM }, 0 }, + { Bad_Opcode }, + { "t2rpntlvwz1rst1", { TMM, MVexSIBMEM }, 0 }, + }, + /* PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0 */ { { "tdpbf8ps", { TMM, Rtmm, VexTmm }, 0 }, @@ -4664,6 +4704,12 @@ static const struct dis386 x86_64_table[][2] = { { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) }, }, + /* X86_64_VEX_0F384A */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F384A_X86_64) }, + }, + /* X86_64_VEX_0F384B */ { { Bad_Opcode }, @@ -4718,6 +4764,18 @@ static const struct dis386 x86_64_table[][2] = { { "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + /* X86_64_VEX_MAP5_F8 */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_MAP5_F8_X86_64) }, + }, + + /* X86_64_VEX_MAP5_F9 */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_MAP5_F9_X86_64) }, + }, + /* X86_64_VEX_MAP5_FD */ { { Bad_Opcode }, @@ -6579,7 +6637,7 @@ static const struct dis386 vex_table[][256] = { /* 48 */ { X86_64_TABLE (X86_64_VEX_0F3848) }, { X86_64_TABLE (X86_64_VEX_0F3849) }, - { Bad_Opcode }, + { X86_64_TABLE (X86_64_VEX_0F384A) }, { X86_64_TABLE (X86_64_VEX_0F384B) }, { Bad_Opcode }, { Bad_Opcode }, @@ -7267,6 +7325,11 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) }, }, + /* VEX_LEN_0F384A_X86_64_W_0 */ + { + { PREFIX_TABLE (PREFIX_VEX_0F384A_X86_64_W_0_L_0) }, + }, + /* VEX_LEN_0F384B_X86_64 */ { { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) }, @@ -7514,6 +7577,16 @@ static const struct dis386 vex_len_table[][2] = { { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, }, + /* VEX_LEN_MAP5_F8_X86_64_M_0 */ + { + { VEX_W_TABLE (VEX_W_MAP5_F8_X86_64_M_0_L_0) }, + }, + + /* VEX_LEN_MAP5_F9_X86_64_M_0 */ + { + { VEX_W_TABLE (VEX_W_MAP5_F9_X86_64_M_0_L_0) }, + }, + /* VEX_LEN_MAP5_FD_X86_64 */ { { VEX_W_TABLE (VEX_W_MAP5_FD_X86_64_L_0) }, @@ -7961,6 +8034,10 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3849_X86_64_L_0 */ { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) }, }, + { + /* VEX_W_0F384A_X86_64 */ + { VEX_LEN_TABLE (VEX_LEN_0F384A_X86_64_W_0) }, + }, { /* VEX_W_0F384B_X86_64_L_0 */ { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) }, @@ -8155,6 +8232,14 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3ADE */ { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, }, + { + /* VEX_W_MAP5_F8_X86_64_M_0 */ + { PREFIX_TABLE (PREFIX_VEX_MAP5_F8_X86_64_M_0_L_0_W_0) }, + }, + { + /* VEX_W_MAP5_F9_X86_64_M_0 */ + { PREFIX_TABLE (PREFIX_VEX_MAP5_F9_X86_64_M_0_L_0_W_0) }, + }, { /* VEX_W_MAP5_FD_X86_64 */ { PREFIX_TABLE (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0) }, @@ -8540,6 +8625,14 @@ static const struct dis386 mod_table[][2] = { /* MOD_VEX_0F386F_X86_64 */ { VEX_LEN_TABLE (VEX_LEN_0F386F_X86_64_M_0) }, }, + { + /* MOD_VEX_MAP5_F8_X86_64 */ + { VEX_LEN_TABLE (VEX_LEN_MAP5_F8_X86_64_M_0) }, + }, + { + /* MOD_VEX_MAP5_F9_X86_64 */ + { VEX_LEN_TABLE (VEX_LEN_MAP5_F9_X86_64_M_0) }, + }, #include "i386-dis-evex-mod.h" }; @@ -8929,6 +9022,8 @@ static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; /* Fetch error indicator. */ static const struct dis386 err_opcode = { NULL, { XX }, 0 }; +static const struct dis386 map5_f8_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_F8) }; +static const struct dis386 map5_f9_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_F9) }; static const struct dis386 map5_fd_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_FD) }; static const struct dis386 map7_f6_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F6) }; static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }; @@ -9250,7 +9345,14 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) else if (vindex == 0xf6) dp = &map7_f6_opcode; else if (vindex == 0xf8) - dp = &map7_f8_opcode; + { + if (vex_table_index == VEX_MAP5) + dp = &map5_f8_opcode; + else + dp = &map7_f8_opcode; + } + else if (vindex == 0xf9) + dp = &map5_f9_opcode; else if (vindex == 0xfd) dp = &map5_fd_opcode; else diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 9824d7a0bd1..2c5ab23cc4a 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -271,6 +271,8 @@ static const dependency isa_dependencies[] = "AMX_TILE" }, { "AMX_FP8", "AMX_TILE" }, + { "AMX_MOVRS", + "AMX_TILE" }, { "KL", "SSE2" }, { "WIDEKL", @@ -441,6 +443,7 @@ static bitfield cpu_flags[] = BITFIELD (AMX_TRANSPOSE), BITFIELD (AMX_TF32), BITFIELD (AMX_FP8), + BITFIELD (AMX_MOVRS), BITFIELD (AMX_TILE), BITFIELD (MOVDIRI), BITFIELD (MOVDIR64B), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 32d5955e680..30db0f8446c 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -256,6 +256,8 @@ enum i386_cpu CpuAMX_TF32, /* AMX-FP8 instructions required */ CpuAMX_FP8, + /* AMX-MOVRS Instructions support required. */ + CpuAMX_MOVRS, /* AMX-TILE instructions required */ CpuAMX_TILE, /* GFNI instructions required */ @@ -509,6 +511,7 @@ typedef union i386_cpu_flags unsigned int cpuamx_complex:1; unsigned int cpuamx_tf32:1; unsigned int cpuamx_fp8:1; + unsigned int cpuamx_movrs:1; unsigned int cpuamx_tile:1; unsigned int cpugfni:1; unsigned int cpuvaes:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 2f7d6de6888..0c5ec201f73 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3235,9 +3235,15 @@ tdpbhf8ps, 0xf2fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, Re tdphbf8ps, 0xf3fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } tdphf8ps, 0x66fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM } +t2rpntlvwrs, 0xf8 | , AMX_MOVRS&AMX_TRANSPOSE, Sibmem|Vex128|Map5|VexW0|NoSuf|ImplicitGroup, { Unspecified|BaseIndex, RegTMM } +t2rpntlvwrs, 0xf8 | , APX_F&AMX_MOVRS&AMX_TRANSPOSE, Sibmem|EVex128|Map5|VexW0|NoSuf|ImplicitGroup, { Unspecified|BaseIndex, RegTMM } + +tileloaddrs, 0xf24a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +tileloaddrst1, 0x664a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } + // AMX instructions end. // KEYLOCKER instructions.