[v2,0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

Message ID	20230912142420.767433-1-mary.bennett@embecosm.com
Headers	DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 788A23854179 From: Mary Bennett <mary.bennett@embecosm.com> To: binutils@sourceware.org Cc: kito.cheng@gmail.com, nelson@rivosinc.com, research_trasio@irq.a4lg.com Subject: [PATCH v2 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Date: Tue, 12 Sep 2023 15:24:18 +0100 Message-Id: <20230912142420.767433-1-mary.bennett@embecosm.com> In-Reply-To: <20230905145300.652455-1-mary.bennett@embecosm.com> References: <20230905145300.652455-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" <binutils-bounces+patchwork=sourceware.org@sourceware.org>
Series	RISC-V: Support CORE-V XCVMAC and XCVALU extensions \| [v2,0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions [v2,1/2] RISC-V: Add support for XCVmac extension in CV32E40P [v2,2/2] RISC-V: Add support for XCValu extension in CV32E40P

Message ID

20230912142420.767433-1-mary.bennett@embecosm.com

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DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 788A23854179
From: Mary Bennett <mary.bennett@embecosm.com>
To: binutils@sourceware.org
Cc: kito.cheng@gmail.com,
	nelson@rivosinc.com,
	research_trasio@irq.a4lg.com
Subject: [PATCH v2 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
Date: Tue, 12 Sep 2023 15:24:18 +0100
Message-Id: <20230912142420.767433-1-mary.bennett@embecosm.com>
In-Reply-To: <20230905145300.652455-1-mary.bennett@embecosm.com>
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Series

RISC-V: Support CORE-V XCVMAC and XCVALU extensions |

Message

Mary Bennett Sept. 12, 2023, 2:24 p.m. UTC

  Changes: v1 -> v2
 - Added MASK_<INSN> for each instruction, as suggested
 - Changed operand 'x' to operand 'X', as suggested

This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V instructions are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

[2] github.com/openhwgroup/corev-binutils-gdb

Contributors:
      Mary Bennett <mary.bennett@embecosm.com>
      Nandni Jamnadas <nandni.jamnadas@embecosm.com>
      Pietra Ferreira <pietra.ferreira@embecosm.com>
      Charlie Keaney
      Jessica Mills
      Craig Blackmore <craig.blackmore@embecosm.com>
      Simon Cook <simon.cook@embecosm.com>
      Jeremy Bennett <jeremy.bennett@embecosm.com>
      Helene Chelin <helene.chelin@embecosm.com>


  RISC-V: Add support for XCValu extension in CV32E40P
  RISC-V: Add support for XCVmac extension in CV32E40P

 bfd/elfxx-riscv.c                             |  11 ++
 gas/config/tc-riscv.c                         |  42 +++++
 gas/doc/c-riscv.texi                          |  10 ++
 gas/testsuite/gas/riscv/cv-alu-boundaries.d   |   3 +
 gas/testsuite/gas/riscv/cv-alu-boundaries.l   |  14 ++
 gas/testsuite/gas/riscv/cv-alu-boundaries.s   |  27 +++
 gas/testsuite/gas/riscv/cv-alu-fail-march.d   |   3 +
 gas/testsuite/gas/riscv/cv-alu-fail-march.l   |  32 ++++
 gas/testsuite/gas/riscv/cv-alu-fail-march.s   |  33 ++++
 .../gas/riscv/cv-alu-fail-operand-01.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-01.l        |  32 ++++
 .../gas/riscv/cv-alu-fail-operand-01.s        |  33 ++++
 .../gas/riscv/cv-alu-fail-operand-02.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-02.l        |  32 ++++
 .../gas/riscv/cv-alu-fail-operand-02.s        |  33 ++++
 .../gas/riscv/cv-alu-fail-operand-03.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-03.l        |  25 +++
 .../gas/riscv/cv-alu-fail-operand-03.s        |  26 +++
 .../gas/riscv/cv-alu-fail-operand-04.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-04.l        |   3 +
 .../gas/riscv/cv-alu-fail-operand-04.s        |   4 +
 .../gas/riscv/cv-alu-fail-operand-05.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-05.l        |   9 +
 .../gas/riscv/cv-alu-fail-operand-05.s        |  10 ++
 .../gas/riscv/cv-alu-fail-operand-06.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-06.l        |   9 +
 .../gas/riscv/cv-alu-fail-operand-06.s        |  10 ++
 .../gas/riscv/cv-alu-fail-operand-07.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-07.l        |  33 ++++
 .../gas/riscv/cv-alu-fail-operand-07.s        |  34 ++++
 gas/testsuite/gas/riscv/cv-alu-insns.d        | 102 ++++++++++++
 gas/testsuite/gas/riscv/cv-alu-insns.s        | 124 ++++++++++++++
 gas/testsuite/gas/riscv/cv-mac-fail-march.d   |   3 +
 gas/testsuite/gas/riscv/cv-mac-fail-march.l   |  23 +++
 gas/testsuite/gas/riscv/cv-mac-fail-march.s   |  24 +++
 gas/testsuite/gas/riscv/cv-mac-fail-operand.d |   3 +
 gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
 gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
 gas/testsuite/gas/riscv/cv-mac-insns.d        |  87 ++++++++++
 gas/testsuite/gas/riscv/cv-mac-insns.s        |  81 +++++++++
 include/opcode/riscv-opc.h                    | 104 ++++++++++++
 include/opcode/riscv.h                        |  12 ++
 opcodes/riscv-dis.c                           |  13 ++
 opcodes/riscv-opc.c                           |  61 +++++++
 44 files changed, 1429 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s

Comments

Mary Bennett Oct. 2, 2023, 2:02 a.m. UTC | #1

Changes: v2 -> v3
 - Rebase against 7a5fa3dbe555794ce401a7435cb91f8695fc9847.

Changes: v1 -> v2
 - Added MASK_<INSN> for each instruction, as suggested.
 - Changed operand 'x' to operand 'X', as suggested.

This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V instructions are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

[2] github.com/openhwgroup/corev-binutils-gdb

Contributors:
      Mary Bennett <mary.bennett@embecosm.com>
      Nandni Jamnadas <nandni.jamnadas@embecosm.com>
      Pietra Ferreira <pietra.ferreira@embecosm.com>
      Charlie Keaney
      Jessica Mills
      Craig Blackmore <craig.blackmore@embecosm.com>
      Simon Cook <simon.cook@embecosm.com>
      Jeremy Bennett <jeremy.bennett@embecosm.com>
      Helene Chelin <helene.chelin@embecosm.com>


  RISC-V: Add support for XCValu extension in CV32E40P
  RISC-V: Add support for XCVmac extension in CV32E40P

 bfd/elfxx-riscv.c                             |  11 ++
 gas/config/tc-riscv.c                         |  42 ++++-
 gas/doc/c-riscv.texi                          |  10 ++
 gas/testsuite/gas/riscv/cv-alu-boundaries.d   |   3 +
 gas/testsuite/gas/riscv/cv-alu-boundaries.l   |  14 ++
 gas/testsuite/gas/riscv/cv-alu-boundaries.s   |  27 +++
 gas/testsuite/gas/riscv/cv-alu-fail-march.d   |   3 +
 gas/testsuite/gas/riscv/cv-alu-fail-march.l   |  32 ++++
 gas/testsuite/gas/riscv/cv-alu-fail-march.s   |  33 ++++
 .../gas/riscv/cv-alu-fail-operand-01.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-01.l        |  32 ++++
 .../gas/riscv/cv-alu-fail-operand-01.s        |  33 ++++
 .../gas/riscv/cv-alu-fail-operand-02.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-02.l        |  32 ++++
 .../gas/riscv/cv-alu-fail-operand-02.s        |  33 ++++
 .../gas/riscv/cv-alu-fail-operand-03.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-03.l        |  25 +++
 .../gas/riscv/cv-alu-fail-operand-03.s        |  26 +++
 .../gas/riscv/cv-alu-fail-operand-04.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-04.l        |   3 +
 .../gas/riscv/cv-alu-fail-operand-04.s        |   4 +
 .../gas/riscv/cv-alu-fail-operand-05.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-05.l        |   9 +
 .../gas/riscv/cv-alu-fail-operand-05.s        |  10 ++
 .../gas/riscv/cv-alu-fail-operand-06.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-06.l        |   9 +
 .../gas/riscv/cv-alu-fail-operand-06.s        |  10 ++
 .../gas/riscv/cv-alu-fail-operand-07.d        |   3 +
 .../gas/riscv/cv-alu-fail-operand-07.l        |  33 ++++
 .../gas/riscv/cv-alu-fail-operand-07.s        |  34 ++++
 gas/testsuite/gas/riscv/cv-alu-insns.d        | 102 ++++++++++++
 gas/testsuite/gas/riscv/cv-alu-insns.s        | 124 ++++++++++++++
 gas/testsuite/gas/riscv/cv-mac-fail-march.d   |   3 +
 gas/testsuite/gas/riscv/cv-mac-fail-march.l   |  23 +++
 gas/testsuite/gas/riscv/cv-mac-fail-march.s   |  24 +++
 gas/testsuite/gas/riscv/cv-mac-fail-operand.d |   3 +
 gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
 gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
 gas/testsuite/gas/riscv/cv-mac-insns.d        |  87 ++++++++++
 gas/testsuite/gas/riscv/cv-mac-insns.s        |  81 +++++++++
 include/opcode/riscv-opc.h                    | 104 ++++++++++++
 include/opcode/riscv.h                        |  12 ++
 opcodes/riscv-dis.c                           |  14 +-
 opcodes/riscv-opc.c                           |  61 +++++++
 44 files changed, 1428 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
 create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
 create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s

Mary Bennett Nov. 6, 2023, 5:27 p.m. UTC | #2

Hi

I'm wondering if there are any other changes required for these patches? 
If not, are they all good to merge?

Kind regards,

Mary

On 02/10/2023 03:02, Mary Bennett wrote:
> Changes: v2 -> v3
>   - Rebase against 7a5fa3dbe555794ce401a7435cb91f8695fc9847.
>
> Changes: v1 -> v2
>   - Added MASK_<INSN> for each instruction, as suggested.
>   - Changed operand 'x' to operand 'X', as suggested.
>
> This patch series presents the comprehensive implementation of the MAC and ALU
> extension for CORE-V.
>
> Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
> ensure its correctness and compatibility with the existing codebase.
> However, your input, reviews, and suggestions are invaluable in making this
> extension even more robust.
>
> The CORE-V instructions are described in the specification [1] and work can be
> found in the OpenHW group's Github repository [2].
>
> [1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
> [2] github.com/openhwgroup/corev-binutils-gdb
>
> Contributors:
>        Mary Bennett <mary.bennett@embecosm.com>
>        Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>        Pietra Ferreira <pietra.ferreira@embecosm.com>
>        Charlie Keaney
>        Jessica Mills
>        Craig Blackmore <craig.blackmore@embecosm.com>
>        Simon Cook <simon.cook@embecosm.com>
>        Jeremy Bennett <jeremy.bennett@embecosm.com>
>        Helene Chelin <helene.chelin@embecosm.com>
>
>
>    RISC-V: Add support for XCValu extension in CV32E40P
>    RISC-V: Add support for XCVmac extension in CV32E40P
>
>   bfd/elfxx-riscv.c                             |  11 ++
>   gas/config/tc-riscv.c                         |  42 ++++-
>   gas/doc/c-riscv.texi                          |  10 ++
>   gas/testsuite/gas/riscv/cv-alu-boundaries.d   |   3 +
>   gas/testsuite/gas/riscv/cv-alu-boundaries.l   |  14 ++
>   gas/testsuite/gas/riscv/cv-alu-boundaries.s   |  27 +++
>   gas/testsuite/gas/riscv/cv-alu-fail-march.d   |   3 +
>   gas/testsuite/gas/riscv/cv-alu-fail-march.l   |  32 ++++
>   gas/testsuite/gas/riscv/cv-alu-fail-march.s   |  33 ++++
>   .../gas/riscv/cv-alu-fail-operand-01.d        |   3 +
>   .../gas/riscv/cv-alu-fail-operand-01.l        |  32 ++++
>   .../gas/riscv/cv-alu-fail-operand-01.s        |  33 ++++
>   .../gas/riscv/cv-alu-fail-operand-02.d        |   3 +
>   .../gas/riscv/cv-alu-fail-operand-02.l        |  32 ++++
>   .../gas/riscv/cv-alu-fail-operand-02.s        |  33 ++++
>   .../gas/riscv/cv-alu-fail-operand-03.d        |   3 +
>   .../gas/riscv/cv-alu-fail-operand-03.l        |  25 +++
>   .../gas/riscv/cv-alu-fail-operand-03.s        |  26 +++
>   .../gas/riscv/cv-alu-fail-operand-04.d        |   3 +
>   .../gas/riscv/cv-alu-fail-operand-04.l        |   3 +
>   .../gas/riscv/cv-alu-fail-operand-04.s        |   4 +
>   .../gas/riscv/cv-alu-fail-operand-05.d        |   3 +
>   .../gas/riscv/cv-alu-fail-operand-05.l        |   9 +
>   .../gas/riscv/cv-alu-fail-operand-05.s        |  10 ++
>   .../gas/riscv/cv-alu-fail-operand-06.d        |   3 +
>   .../gas/riscv/cv-alu-fail-operand-06.l        |   9 +
>   .../gas/riscv/cv-alu-fail-operand-06.s        |  10 ++
>   .../gas/riscv/cv-alu-fail-operand-07.d        |   3 +
>   .../gas/riscv/cv-alu-fail-operand-07.l        |  33 ++++
>   .../gas/riscv/cv-alu-fail-operand-07.s        |  34 ++++
>   gas/testsuite/gas/riscv/cv-alu-insns.d        | 102 ++++++++++++
>   gas/testsuite/gas/riscv/cv-alu-insns.s        | 124 ++++++++++++++
>   gas/testsuite/gas/riscv/cv-mac-fail-march.d   |   3 +
>   gas/testsuite/gas/riscv/cv-mac-fail-march.l   |  23 +++
>   gas/testsuite/gas/riscv/cv-mac-fail-march.s   |  24 +++
>   gas/testsuite/gas/riscv/cv-mac-fail-operand.d |   3 +
>   gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
>   gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
>   gas/testsuite/gas/riscv/cv-mac-insns.d        |  87 ++++++++++
>   gas/testsuite/gas/riscv/cv-mac-insns.s        |  81 +++++++++
>   include/opcode/riscv-opc.h                    | 104 ++++++++++++
>   include/opcode/riscv.h                        |  12 ++
>   opcodes/riscv-dis.c                           |  14 +-
>   opcodes/riscv-opc.c                           |  61 +++++++
>   44 files changed, 1428 insertions(+), 2 deletions(-)
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
>   create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
>   create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
>   create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
>
-- 
Embecosm Limited
22 London Road
Southampton
SO15 2AF
Registered Number: 6577021.
Registered in England & Wales.

Name: Mary Bennett
Title: Compiler Tool Chain Engineer
Phone: 07802418997
Website: www.embecosm.com

Nelson Chu Nov. 7, 2023, 4:12 a.m. UTC | #3

On Tue, Nov 7, 2023 at 1:27 AM Mary Bennett <mary.bennett@embecosm.com>
wrote:

> Hi
>
> I'm wondering if there are any other changes required for these patches?
> If not, are they all good to merge?
>
> Kind regards,
>
> Mary
>

No, at least looks good to me, so committed.  We can update them if any
changes are needed in the future patches.

Thanks for contributing the vendor stuffs to upstream
Nelson