From patchwork Tue Sep 12 14:24:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mary Bennett X-Patchwork-Id: 56119 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 314443864C69 for ; Tue, 12 Sep 2023 14:25:03 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by sourceware.org (Postfix) with ESMTPS id 788A23854179 for ; Tue, 12 Sep 2023 14:24:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 788A23854179 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-31ae6bf91a9so5760796f8f.2 for ; Tue, 12 Sep 2023 07:24:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1694528684; x=1695133484; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B8JIG/khKFjW+PUL2xqzIbRSBOtjOfn23l23CxOW98g=; b=HZ56oHoixSQAyeRHUfoRRE6Ke4UZf/Iclgy0A8AC8yUI+4nOZHkk4bjbM81qVj2QL7 6Mfsq1b9Gni3ioi2TGKipYXCtDyZlGLku1hUrI30xy9h6QLQpSQD09pz3mzgqVv3wzUQ 9NKChHmbwdQswMEMdjMbJPRlz0oYh1loNCN0wVOfEE9WVSqk65Ve3Rs5nWowoOQUPlC+ EHONpjBD61pTNndbukG9IxpJ7m28RBZd6JhhVbNCmjxt8iHovabLWB9+qTDe4FP9teaQ fB63cZoOuFVjkPL9aj5JRB9Q0iCKD7Ml3FD8gofbBmBfOuHyGcKisz0v8ohDN2OCjgKc CBBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694528684; x=1695133484; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B8JIG/khKFjW+PUL2xqzIbRSBOtjOfn23l23CxOW98g=; b=Z0RR9TONQlZ6iCgn2zkWctMWV+fMxXuLAYb4tCzZi7mpymxJwdKKhMuITQdpVyXXrH aMTyTOVNBVXjkJildgEVhk33eJxbiiK6DaWNJD3KzLEPmJ9x6ba2y96X0PI1e7OOMZ7l vBaftnpp9DDfg46aBbqcbgT93CIK9VdvlfnHx218jqdK9+fDAoyC9RMhnBJyqpzDlKiY dXMAG2ghwkTMtn4Z+mex0azju/cDI7w80KtGEaG8k3YZ1MwSZo1NzVDLeGvnOAwrpTrT YaBYjnYfo/bBrW9dsyWbflr7nucuaLfBNd7dWbN9atm8DgfSYew2Cg/SEjKZo4ChT/YQ mnsg== X-Gm-Message-State: AOJu0YwQzFVD8t4msEBq5tU9HodZ9cSxZ9dLvmNmpiUvXlVottNGFVxa GQkpSNczfRzj096Wd+qvWtdGV9d3p/ZvPLD/LJ047g== X-Google-Smtp-Source: AGHT+IEjUEmX6ncDnZyBb41vh/OzyHEpdhKPPBywfSgjJC/PB3xAjCEqc/9Lw6hrtqpeRS/w/qBq2w== X-Received: by 2002:a5d:6d87:0:b0:31f:84a3:d188 with SMTP id l7-20020a5d6d87000000b0031f84a3d188mr11416586wrs.22.1694528683522; Tue, 12 Sep 2023 07:24:43 -0700 (PDT) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id n3-20020a5d4203000000b0031c3ee933b5sm12859758wrq.108.2023.09.12.07.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 07:24:43 -0700 (PDT) From: Mary Bennett To: binutils@sourceware.org Cc: kito.cheng@gmail.com, nelson@rivosinc.com, research_trasio@irq.a4lg.com Subject: [PATCH v2 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Date: Tue, 12 Sep 2023 15:24:18 +0100 Message-Id: <20230912142420.767433-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905145300.652455-1-mary.bennett@embecosm.com> References: <20230905145300.652455-1-mary.bennett@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" Changes: v1 -> v2 - Added MASK_ for each instruction, as suggested - Changed operand 'x' to operand 'X', as suggested This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V instructions are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html [2] github.com/openhwgroup/corev-binutils-gdb Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCValu extension in CV32E40P RISC-V: Add support for XCVmac extension in CV32E40P bfd/elfxx-riscv.c | 11 ++ gas/config/tc-riscv.c | 42 +++++ gas/doc/c-riscv.texi | 10 ++ gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 + gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++ gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++ gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 + gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++ gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++ .../gas/riscv/cv-alu-fail-operand-01.d | 3 + .../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++ .../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++ .../gas/riscv/cv-alu-fail-operand-02.d | 3 + .../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++ .../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++ .../gas/riscv/cv-alu-fail-operand-03.d | 3 + .../gas/riscv/cv-alu-fail-operand-03.l | 25 +++ .../gas/riscv/cv-alu-fail-operand-03.s | 26 +++ .../gas/riscv/cv-alu-fail-operand-04.d | 3 + .../gas/riscv/cv-alu-fail-operand-04.l | 3 + .../gas/riscv/cv-alu-fail-operand-04.s | 4 + .../gas/riscv/cv-alu-fail-operand-05.d | 3 + .../gas/riscv/cv-alu-fail-operand-05.l | 9 + .../gas/riscv/cv-alu-fail-operand-05.s | 10 ++ .../gas/riscv/cv-alu-fail-operand-06.d | 3 + .../gas/riscv/cv-alu-fail-operand-06.l | 9 + .../gas/riscv/cv-alu-fail-operand-06.s | 10 ++ .../gas/riscv/cv-alu-fail-operand-07.d | 3 + .../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++ .../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++ gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++ gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++ gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 + gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++ gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++ gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 + gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++ gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++ gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++ gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++ include/opcode/riscv-opc.h | 104 ++++++++++++ include/opcode/riscv.h | 12 ++ opcodes/riscv-dis.c | 13 ++ opcodes/riscv-opc.c | 61 +++++++ 44 files changed, 1429 insertions(+) create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s