diff mbox

aarch64 testsuite patch for ILP32

Message ID 201702031950.v13JoiPq020912@sellcey-dt.caveonetworks.com
State New, archived
Headers

Commit Message

Steve Ellcey Feb. 3, 2017, 7:50 p.m. UTC 
  While working on aarch64 ILP32 support for gdb I ran into two tests that
contain aarch64 inline assembly and that do not work when run in ILP32
mode.  I would like to check in this patch even though the ILP32 support
is not yet in gdb.  That way I can minimize the subsequent patch to support
ILP32 mode.  This change also fixes a latent bug that is in aarch64-fp.c.
The instructions that load q0 and q1 assume the address they want to use
is in register x0 but the code does not gaurantee that.  It happens to
work because we do not optimize the compilation and GCC uses x0 as a temporary
register in the earlier statement but that is just sheer luck.  I have fixed
this by adding a read argument to the load instructions to ensure they have
the right value.

Tested in ILP32 and LP64 modes on aarch64.  OK to checkin?

Steve Ellcey
sellcey@cavium.com


2017-02-03  Steve Ellcey  <sellcey@cavium.com>

	* gdb.arch/aarch64-atomic-inst.c: Include stdint.h, use uint64_t
	instead of long for 64 bit types.
	* gdb.arch/aarch64-fp.c (main): Use %w0 instead of %x0 in 32
	bit mode.  Specify input register for ldr of q0 and q1.

Comments

Yao Qi Feb. 6, 2017, 10 a.m. UTC | #1 
On 17-02-03 11:50:44, Steve Ellcey wrote:
> While working on aarch64 ILP32 support for gdb I ran into two tests that
> contain aarch64 inline assembly and that do not work when run in ILP32
> mode.  I would like to check in this patch even though the ILP32 support
> is not yet in gdb.  That way I can minimize the subsequent patch to support
> ILP32 mode.  This change also fixes a latent bug that is in aarch64-fp.c.
> The instructions that load q0 and q1 assume the address they want to use
> is in register x0 but the code does not gaurantee that.  It happens to
> work because we do not optimize the compilation and GCC uses x0 as a temporary
> register in the earlier statement but that is just sheer luck.  I have fixed
> this by adding a read argument to the load instructions to ensure they have
> the right value.

The bug fix part can go in now if you want to split it out this patch, but
ILP32 related part should go in with your ILP32 patch.

> 
> Tested in ILP32 and LP64 modes on aarch64.  OK to checkin?
> 
> Steve Ellcey
> sellcey@cavium.com
> 
> 
> 2017-02-03  Steve Ellcey  <sellcey@cavium.com>
> 
> 	* gdb.arch/aarch64-atomic-inst.c: Include stdint.h, use uint64_t
> 	instead of long for 64 bit types.
> 	* gdb.arch/aarch64-fp.c (main): Use %w0 instead of %x0 in 32
> 	bit mode.  Specify input register for ldr of q0 and q1.

Patch is OK, but should go in with your ILP32 patch.
diff mbox

Patch

diff --git a/gdb/testsuite/gdb.arch/aarch64-atomic-inst.c b/gdb/testsuite/gdb.arch/aarch64-atomic-inst.c
index 4358252..0c1f557 100644
--- a/gdb/testsuite/gdb.arch/aarch64-atomic-inst.c
+++ b/gdb/testsuite/gdb.arch/aarch64-atomic-inst.c
@@ -15,10 +15,12 @@ 
    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
+#include <stdint.h>
+
 int main(void)
 {
-  unsigned long tmp, cond;
-  unsigned long dword = 0;
+  uint64_t tmp, cond;
+  uint64_t dword = 0;
 
   /* Test that we can step over ldxr/stxr. This sequence should step from
      ldxr to the following __asm __volatile.  */
diff --git a/gdb/testsuite/gdb.arch/aarch64-fp.c b/gdb/testsuite/gdb.arch/aarch64-fp.c
index 5507de8..6a8f8bc 100644
--- a/gdb/testsuite/gdb.arch/aarch64-fp.c
+++ b/gdb/testsuite/gdb.arch/aarch64-fp.c
@@ -26,12 +26,20 @@  main (void)
   void *addr;
     
   addr = &buf0[0];
+#if __LP64__
   __asm __volatile ("ldr %x0, [%1]" : "=r" (val) : "r" (&addr));
-  __asm __volatile ("ldr q0, [x0]");
+#else
+  __asm __volatile ("ldr %w0, [%1]" : "=r" (val) : "r" (&addr));
+#endif
+  __asm __volatile ("ldr q0, [%x0]" : : "r" (val));
    
   addr = &buf1[0];
+#if __LP64__
   __asm __volatile ("ldr %x0, [%1]" : "=r" (val) : "r" (&addr));
-  __asm __volatile ("ldr q1, [x0]");
+#else
+  __asm __volatile ("ldr %w0, [%1]" : "=r" (val) : "r" (&addr));
+#endif
+  __asm __volatile ("ldr q1, [%x0]" : : "r" (val));
   
   return 1;
 }