[1/3] gdb, doc: Fix AVX-512 documentation.
Checks
Context |
Check |
Description |
linaro-tcwg-bot/tcwg_gdb_build--master-aarch64 |
success
|
Testing passed
|
linaro-tcwg-bot/tcwg_gdb_build--master-arm |
success
|
Testing passed
|
linaro-tcwg-bot/tcwg_gdb_check--master-arm |
success
|
Testing passed
|
linaro-tcwg-bot/tcwg_gdb_check--master-aarch64 |
success
|
Testing passed
|
Commit Message
org.gnu.gdb.i386.avx512 adds k registers, but these aren't mentioned in the
docs yet. Fix that.
In addition the documentation describes xmm registers with an `h`
(e.g. xmm16h). I am assuming that we follow the register xml files here,
which don't have the h suffix. So this removes that as well.
---
gdb/doc/gdb.texinfo | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
Comments
> From: Felix Willgerodt <felix.willgerodt@intel.com>
> Date: Thu, 23 May 2024 15:48:40 +0200
>
> org.gnu.gdb.i386.avx512 adds k registers, but these aren't mentioned in the
> docs yet. Fix that.
>
> In addition the documentation describes xmm registers with an `h`
> (e.g. xmm16h). I am assuming that we follow the register xml files here,
> which don't have the h suffix. So this removes that as well.
> ---
> gdb/doc/gdb.texinfo | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
> index 61f91ef4ad6..750f368f980 100644
> --- a/gdb/doc/gdb.texinfo
> +++ b/gdb/doc/gdb.texinfo
> @@ -49471,7 +49471,7 @@ describe additional @sc{xmm} registers:
>
> @itemize @minus
> @item
> -@samp{xmm16h} through @samp{xmm31h}, only valid for amd64.
> +@samp{xmm16} through @samp{xmm31}, only valid for amd64.
> @end itemize
>
> It should describe the upper 128 bits of additional @sc{ymm} registers:
> @@ -49499,6 +49499,14 @@ describe the additional @sc{zmm} registers:
> @samp{zmm16h} through @samp{zmm31h}, only valid for amd64.
> @end itemize
>
> +It should
> +describe the additional 64-bit @sc{k} registers:
> +
> +@itemize @minus
> +@item
> +@samp{k0} through @samp{k7}, valid for amd64 and i386.
> +@end itemize
> +
> The @samp{org.gnu.gdb.i386.pkeys} feature is optional. It should
> describe a single register, @samp{pkru}. It is a 32-bit register
> valid for i386 and amd64.
> --
> 2.34.1
This is okay, thanks.
Approved-By: Eli Zaretskii <eliz@gnu.org>
> > From: Felix Willgerodt <felix.willgerodt@intel.com>
> > Date: Thu, 23 May 2024 15:48:40 +0200
> >
> > org.gnu.gdb.i386.avx512 adds k registers, but these aren't mentioned in the
> > docs yet. Fix that.
> >
> > In addition the documentation describes xmm registers with an `h`
> > (e.g. xmm16h). I am assuming that we follow the register xml files here,
> > which don't have the h suffix. So this removes that as well.
> > ---
> > gdb/doc/gdb.texinfo | 10 +++++++++-
> > 1 file changed, 9 insertions(+), 1 deletion(-)
> >
> This is okay, thanks.
>
> Approved-By: Eli Zaretskii <eliz@gnu.org>
Thanks, I pushed this.
Felix
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
@@ -49471,7 +49471,7 @@ describe additional @sc{xmm} registers:
@itemize @minus
@item
-@samp{xmm16h} through @samp{xmm31h}, only valid for amd64.
+@samp{xmm16} through @samp{xmm31}, only valid for amd64.
@end itemize
It should describe the upper 128 bits of additional @sc{ymm} registers:
@@ -49499,6 +49499,14 @@ describe the additional @sc{zmm} registers:
@samp{zmm16h} through @samp{zmm31h}, only valid for amd64.
@end itemize
+It should
+describe the additional 64-bit @sc{k} registers:
+
+@itemize @minus
+@item
+@samp{k0} through @samp{k7}, valid for amd64 and i386.
+@end itemize
+
The @samp{org.gnu.gdb.i386.pkeys} feature is optional. It should
describe a single register, @samp{pkru}. It is a 32-bit register
valid for i386 and amd64.