[v4] x86: Add more feature definitions to isa-level.h
Checks
Context |
Check |
Description |
dj/TryBot-apply_patch |
success
|
Patch applied to master at the time it was sent
|
dj/TryBot-32bit |
success
|
Build for i686
|
Commit Message
This commit doesn't change anything in itself. It is just to add
definitions that will be needed by future patches.
---
sysdeps/x86/isa-level.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
Comments
On Mon, Jun 27, 2022 at 8:49 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> This commit doesn't change anything in itself. It is just to add
> definitions that will be needed by future patches.
> ---
> sysdeps/x86/isa-level.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> index f293aea906..2cbce25840 100644
> --- a/sysdeps/x86/isa-level.h
> +++ b/sysdeps/x86/isa-level.h
> @@ -67,15 +67,29 @@
> /* Depending on the minimum ISA level, a feature check result can be a
> compile-time constant.. */
>
> +
> +/* ISA CPU_FEATURE_USABLE_P defaults. */
What does "defaults" mean? "For X86_ISA_CPU_FEATURE_USABLE_P"?
> +
> /* ISA level >= 4 guaranteed includes. */
> #define AVX512F_X86_ISA_LEVEL 4
> #define AVX512VL_X86_ISA_LEVEL 4
> #define AVX512BW_X86_ISA_LEVEL 4
> +#define AVX512DQ_X86_ISA_LEVEL 4
>
> /* ISA level >= 3 guaranteed includes. */
> #define AVX_X86_ISA_LEVEL 3
> #define AVX2_X86_ISA_LEVEL 3
> #define BMI2_X86_ISA_LEVEL 3
> +#define MOVBE_X86_ISA_LEVEL 3
> +
> +/* ISA level >= 2 guaranteed includes. */
> +#define SSE4_2_X86_ISA_LEVEL 2
> +#define SSSE3_X86_ISA_LEVEL 2
> +
> +
> +/* ISA CPU_FEATURES_ARCH_P defaults. */
"For X86_ISA_CPU_FEATURES_ARCH_P"?
> +
> +/* Isa level >= 3 feature(s) enabled. */
No need for this. Some features may be disabled.
>
> /* NB: This feature is enabled when ISA level >= 3, which was disabled
> for the following CPUs:
> @@ -89,6 +103,9 @@
> when ISA level < 3. */
> #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
>
> +/* Isa level >= 2 feature(s) enabled. */
These are not features in ISAs. "Feature(s) enabled when ISA level >= 2"?
> +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> +
> /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> runtime checks. They differ in two ways.
> --
> 2.34.1
>
On Mon, Jun 27, 2022 at 8:59 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:49 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > This commit doesn't change anything in itself. It is just to add
> > definitions that will be needed by future patches.
> > ---
> > sysdeps/x86/isa-level.h | 17 +++++++++++++++++
> > 1 file changed, 17 insertions(+)
> >
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > index f293aea906..2cbce25840 100644
> > --- a/sysdeps/x86/isa-level.h
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -67,15 +67,29 @@
> > /* Depending on the minimum ISA level, a feature check result can be a
> > compile-time constant.. */
> >
> > +
> > +/* ISA CPU_FEATURE_USABLE_P defaults. */
>
> What does "defaults" mean? "For X86_ISA_CPU_FEATURE_USABLE_P"?
Done in V5
>
> > +
> > /* ISA level >= 4 guaranteed includes. */
> > #define AVX512F_X86_ISA_LEVEL 4
> > #define AVX512VL_X86_ISA_LEVEL 4
> > #define AVX512BW_X86_ISA_LEVEL 4
> > +#define AVX512DQ_X86_ISA_LEVEL 4
> >
> > /* ISA level >= 3 guaranteed includes. */
> > #define AVX_X86_ISA_LEVEL 3
> > #define AVX2_X86_ISA_LEVEL 3
> > #define BMI2_X86_ISA_LEVEL 3
> > +#define MOVBE_X86_ISA_LEVEL 3
> > +
> > +/* ISA level >= 2 guaranteed includes. */
> > +#define SSE4_2_X86_ISA_LEVEL 2
> > +#define SSSE3_X86_ISA_LEVEL 2
> > +
> > +
> > +/* ISA CPU_FEATURES_ARCH_P defaults. */
>
> "For X86_ISA_CPU_FEATURES_ARCH_P"?
Done in V5
>
> > +
> > +/* Isa level >= 3 feature(s) enabled. */
>
> No need for this. Some features may be disabled.
Done in V5
>
> >
> > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > for the following CPUs:
> > @@ -89,6 +103,9 @@
> > when ISA level < 3. */
> > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> >
> > +/* Isa level >= 2 feature(s) enabled. */
>
> These are not features in ISAs. "Feature(s) enabled when ISA level >= 2"?
Done in V5
>
> > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > +
> > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > runtime checks. They differ in two ways.
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
@@ -67,15 +67,29 @@
/* Depending on the minimum ISA level, a feature check result can be a
compile-time constant.. */
+
+/* ISA CPU_FEATURE_USABLE_P defaults. */
+
/* ISA level >= 4 guaranteed includes. */
#define AVX512F_X86_ISA_LEVEL 4
#define AVX512VL_X86_ISA_LEVEL 4
#define AVX512BW_X86_ISA_LEVEL 4
+#define AVX512DQ_X86_ISA_LEVEL 4
/* ISA level >= 3 guaranteed includes. */
#define AVX_X86_ISA_LEVEL 3
#define AVX2_X86_ISA_LEVEL 3
#define BMI2_X86_ISA_LEVEL 3
+#define MOVBE_X86_ISA_LEVEL 3
+
+/* ISA level >= 2 guaranteed includes. */
+#define SSE4_2_X86_ISA_LEVEL 2
+#define SSSE3_X86_ISA_LEVEL 2
+
+
+/* ISA CPU_FEATURES_ARCH_P defaults. */
+
+/* Isa level >= 3 feature(s) enabled. */
/* NB: This feature is enabled when ISA level >= 3, which was disabled
for the following CPUs:
@@ -89,6 +103,9 @@
when ISA level < 3. */
#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+/* Isa level >= 2 feature(s) enabled. */
+#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
+
/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
runtime checks. They differ in two ways.