From patchwork Tue Jun 28 03:49:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 55466 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 89DA3386F0D7 for ; Tue, 28 Jun 2022 03:50:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 89DA3386F0D7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1656388204; bh=F1Znk158tpQpw6t2AMIQ8pk7g4YTGd6pHBKYvDZiDWc=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=DF1vx2gvfmyLFjfXSHtmY5xsRH4qc2Gn0GPe0zp83KKOk44ZpO3c5aX+QmY1RMluX twwsez+B4zKU0hNyngXiLpLhEAcnQ2QgIvxNgSAiFVq/zCNg1nH7Jc8O0QP0o0oaD3 S2AsxywYik59kdXbEQ4Ri1cQAvL4I87cc2idMRF0= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by sourceware.org (Postfix) with ESMTPS id 537B93857BB5 for ; Tue, 28 Jun 2022 03:49:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 537B93857BB5 Received: by mail-pj1-x102d.google.com with SMTP id go6so11374544pjb.0 for ; Mon, 27 Jun 2022 20:49:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F1Znk158tpQpw6t2AMIQ8pk7g4YTGd6pHBKYvDZiDWc=; b=UGBclzfGC6HJd5S8RUh0UjkhN3alhI22hX5GJ8FcSajCUjlRz0IENmzYIRt5vmZfX+ QIxd0juQzvqXb/anAMMZiQ76tnvPXcQF6DQQLkXlHtL9LgG4lVdtl3lyY6Q16vX0Qu8+ 7q6k47GIR8I8G9G6Lf9EzjQ4p/P2lKapxrzksy6vuA0Oz7mtpU4bzeZEKb7zMmyCg+PV 2wy0UuIlTdFX9CCuhf5Og6p5k816R4GAeQZb9ex3yRN8pdEwgMGAsNdQER/FpVgEQ56h Vbk0OgRBEploX1Nj3LUPZBsIlaKbVpNFO9h4ilKgwVT/I8omhDhjx4oqCW/KuHuDYwAK v4fg== X-Gm-Message-State: AJIora81BbRwg3Ls3qmNquruFbxAstLMjYquIsWyvCs0nUfptGbhPNFo PWIN3xwg5IUir46cDxdmVEwOKAozDlQ= X-Google-Smtp-Source: AGRyM1vIZR0cyCW97XfEE5nnaxXjEKiRA6vtuJ28z4xKfsf+WqiikHvyb0T+mJtwZlspJK0l6RY0pQ== X-Received: by 2002:a17:90b:1650:b0:1ec:b5e7:42ae with SMTP id il16-20020a17090b165000b001ecb5e742aemr19528732pjb.15.1656388182192; Mon, 27 Jun 2022 20:49:42 -0700 (PDT) Received: from noah-tgl.. ([2600:1010:b016:fb15:ad7e:a465:b31a:6f06]) by smtp.gmail.com with ESMTPSA id p22-20020a1709027ed600b0016a0fe1a1fbsm8032256plb.220.2022.06.27.20.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 20:49:41 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v4] x86: Add more feature definitions to isa-level.h Date: Mon, 27 Jun 2022 20:49:39 -0700 Message-Id: <20220628034939.2116112-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628010446.3464287-1-goldstein.w.n@gmail.com> References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" This commit doesn't change anything in itself. It is just to add definitions that will be needed by future patches. --- sysdeps/x86/isa-level.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h index f293aea906..2cbce25840 100644 --- a/sysdeps/x86/isa-level.h +++ b/sysdeps/x86/isa-level.h @@ -67,15 +67,29 @@ /* Depending on the minimum ISA level, a feature check result can be a compile-time constant.. */ + +/* ISA CPU_FEATURE_USABLE_P defaults. */ + /* ISA level >= 4 guaranteed includes. */ #define AVX512F_X86_ISA_LEVEL 4 #define AVX512VL_X86_ISA_LEVEL 4 #define AVX512BW_X86_ISA_LEVEL 4 +#define AVX512DQ_X86_ISA_LEVEL 4 /* ISA level >= 3 guaranteed includes. */ #define AVX_X86_ISA_LEVEL 3 #define AVX2_X86_ISA_LEVEL 3 #define BMI2_X86_ISA_LEVEL 3 +#define MOVBE_X86_ISA_LEVEL 3 + +/* ISA level >= 2 guaranteed includes. */ +#define SSE4_2_X86_ISA_LEVEL 2 +#define SSSE3_X86_ISA_LEVEL 2 + + +/* ISA CPU_FEATURES_ARCH_P defaults. */ + +/* Isa level >= 3 feature(s) enabled. */ /* NB: This feature is enabled when ISA level >= 3, which was disabled for the following CPUs: @@ -89,6 +103,9 @@ when ISA level < 3. */ #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 +/* Isa level >= 2 feature(s) enabled. */ +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 + /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P runtime checks. They differ in two ways.