diff mbox series

[2/2] xtensa: Reflect the 32-bit Integer Divide Option

Message ID 5f99c6da-aa0c-5384-ee48-3556a03a6bf0@yahoo.co.jp
State New
Headers
Series [1/2] xtensa: Rename deprecated extv/extzv insn patterns to extvsi/extzvsi |

Commit Message

Takayuki 'January June' Suwa May 6, 2022, 10:34 a.m. UTC 
  On Espressif's ESP8266 (based on Tensilica LX106, no hardware divider),
this patch reduces the size of each:

   __moddi3() @ libgcc.a :  969 -> 301 (saves 668)
   __divmoddi4()         : 1111 -> 426 (saves 685)
   __udivmoddi4()        : 1043 -> 319 (saves 724)

in bytes, respectively.

gcc/ChangeLog:

	* config/xtensa/xtensa.h (TARGET_HAS_NO_HW_DIVIDE): New macro
	definition.
---
  gcc/config/xtensa/xtensa.h | 5 +++++
  1 file changed, 5 insertions(+)

Comments

Max Filippov May 13, 2022, 9:37 a.m. UTC | #1 
On Fri, May 6, 2022 at 3:36 AM Takayuki 'January June' Suwa via
Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> On Espressif's ESP8266 (based on Tensilica LX106, no hardware divider),
> this patch reduces the size of each:
>
>    __moddi3() @ libgcc.a :  969 -> 301 (saves 668)
>    __divmoddi4()         : 1111 -> 426 (saves 685)
>    __udivmoddi4()        : 1043 -> 319 (saves 724)
>
> in bytes, respectively.
>
> gcc/ChangeLog:
>
>         * config/xtensa/xtensa.h (TARGET_HAS_NO_HW_DIVIDE): New macro
>         definition.
> ---
>   gcc/config/xtensa/xtensa.h | 5 +++++
>   1 file changed, 5 insertions(+)

Regtested for target=xtensa-linux-uclibc, there's new regression in
gcc.c-torture/execute/20101011-1.c
related to division by 0 implemented as an invalid opcode exception
that the kernel should convert to division by 0 signal, but does not.
It should be fixed in the kernel.

Committed to master.
diff mbox series

Patch

diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index 00e2930b30a..d25594f0c1f 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -75,6 +75,11 @@  along with GCC; see the file COPYING3.  If not see
  #define HAVE_AS_TLS 0
  #endif

+/* Define this if the target has no hardware divide instructions.  */
+#if !TARGET_DIV32
+#define TARGET_HAS_NO_HW_DIVIDE
+#endif
+
  
  /* Target CPU builtins.  */
  #define TARGET_CPU_CPP_BUILTINS()					\