diff mbox series

[PATCH/committed,13/20] sim: mips: fix -Wimplicit-fallthrough warnings

Message ID 20231221070127.19142-13-vapier@gentoo.org
State New
Headers
Series [PATCH/committed,01/20] sim: signal: mark signal callback funcs as noreturn since they don't return |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gdb_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_gdb_build--master-aarch64 fail Patch failed to apply

Commit Message

Mike Frysinger Dec. 21, 2023, 7:01 a.m. UTC 
  Seems like these cases were meant to fallthru.
---
 sim/mips/cp1.c     | 4 ++++
 sim/mips/interp.c  | 4 +++-
 sim/mips/m16e.igen | 6 ++++++
 3 files changed, 13 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/sim/mips/cp1.c b/sim/mips/cp1.c
index 3e2d5d9f474d..9d1dfe5d8dde 100644
--- a/sim/mips/cp1.c
+++ b/sim/mips/cp1.c
@@ -262,6 +262,7 @@  store_fpr (sim_cpu *cpu,
 	{
 	case fmt_uninterpreted_32:
 	  fmt = fmt_uninterpreted;
+	  ATTRIBUTE_FALLTHROUGH;
 	case fmt_single:
 	case fmt_word:
 	  if (STATE_VERBOSE_P (SD))
@@ -274,6 +275,7 @@  store_fpr (sim_cpu *cpu,
 
 	case fmt_uninterpreted_64:
 	  fmt = fmt_uninterpreted;
+	  ATTRIBUTE_FALLTHROUGH;
 	case fmt_uninterpreted:
 	case fmt_double:
 	case fmt_long:
@@ -294,6 +296,7 @@  store_fpr (sim_cpu *cpu,
 	{
 	case fmt_uninterpreted_32:
 	  fmt = fmt_uninterpreted;
+	  ATTRIBUTE_FALLTHROUGH;
 	case fmt_single:
 	case fmt_word:
 	  FGR[fpr] = (value & 0xFFFFFFFF);
@@ -302,6 +305,7 @@  store_fpr (sim_cpu *cpu,
 
 	case fmt_uninterpreted_64:
 	  fmt = fmt_uninterpreted;
+	  ATTRIBUTE_FALLTHROUGH;
 	case fmt_uninterpreted:
 	case fmt_double:
 	case fmt_long:
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 255807f67906..708e27f6b2b7 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1247,7 +1247,7 @@  sim_monitor (SIM_DESC sd,
 	if (A0 == 0)	/* waitflag == NOWAIT */
 	  V0 = (unsigned_word)-1;
       }
-     /* Drop through to case 11 */
+     ATTRIBUTE_FALLTHROUGH;
 
     case 11: /* char inbyte(void) */
       {
@@ -1904,6 +1904,7 @@  signal_exception (SIM_DESC sd,
 	 }
        /* else fall through to normal exception processing */
        sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
+       ATTRIBUTE_FALLTHROUGH;
      }
 
     default:
@@ -2329,6 +2330,7 @@  decode_coproc (SIM_DESC sd,
 				  "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
 				  (unsigned long)cia);
 		GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
+		ATTRIBUTE_FALLTHROUGH;
 		/* CPR[0,rd] = GPR[rt]; */
 	      default:
 		if (op == cp0_mfc0 || op == cp0_dmfc0)
diff --git a/sim/mips/m16e.igen b/sim/mips/m16e.igen
index fda54cacad99..9facbd47bd61 100644
--- a/sim/mips/m16e.igen
+++ b/sim/mips/m16e.igen
@@ -212,16 +212,22 @@ 
   switch (xsregs) {
   case 7:
     do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]);
+    ATTRIBUTE_FALLTHROUGH;
   case 6:
     do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]);
+    ATTRIBUTE_FALLTHROUGH;
   case 5:
     do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]);
+    ATTRIBUTE_FALLTHROUGH;
   case 4:
     do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]);
+    ATTRIBUTE_FALLTHROUGH;
   case 3:
     do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]);
+    ATTRIBUTE_FALLTHROUGH;
   case 2:
     do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]);
+    ATTRIBUTE_FALLTHROUGH;
   case 1:
     do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]);
   }