diff mbox

[spu] Fix single-stepping regression

Message ID 20171126162440.D0A5FD802F9@oc3748833570.ibm.com
State New
Headers show

Commit Message

Ulrich Weigand Nov. 26, 2017, 4:24 p.m. UTC
Hello,

switching spu_software_single_step to use a regcache instead of a frame:
https://sourceware.org/ml/gdb-patches/2016-11/msg00355.html
caused a serious regression to SPU single-stepping.

There were two separate problems:
- SPU_LSLR_REGNUM is a pseudo register, so we must use the "cooked"
  regcache methods instead of the "raw" ones to access it.
- When accessing a branch target register, we must only use the first
  four bytes of the 16-byte vector register.  This was done automatically
  by the frame routines, but not by the regcache routines.

Bye,
Ulrich


gdb/ChangeLog:
2017-11-26  Ulrich Weigand  <uweigand@de.ibm.com>

	* spu-tdep.c (spu_software_single_step): Access SPU_LSLR_REGNUM as
	"cooked" register.  Access only first four bytes of branch target
	registers.
diff mbox

Patch

diff --git a/gdb/spu-tdep.c b/gdb/spu-tdep.c
index ecdc7fc..34a536a 100644
--- a/gdb/spu-tdep.c
+++ b/gdb/spu-tdep.c
@@ -1632,8 +1632,8 @@  spu_software_single_step (struct regcache *regcache)
   insn = extract_unsigned_integer (buf, 4, byte_order);
 
   /* Get local store limit.  */
-  lslr = regcache_raw_get_unsigned (regcache, SPU_LSLR_REGNUM);
-  if (!lslr)
+  if ((regcache_cooked_read_unsigned (regcache, SPU_LSLR_REGNUM, &lslr)
+       != REG_VALID) || !lslr)
     lslr = (ULONGEST) -1;
 
   /* Next sequential instruction is at PC + 4, except if the current
@@ -1653,7 +1653,10 @@  spu_software_single_step (struct regcache *regcache)
       if (reg == SPU_PC_REGNUM)
 	target += SPUADDR_ADDR (pc);
       else if (reg != -1)
-	target += regcache_raw_get_unsigned (regcache, reg) & -4;
+      {
+	regcache_raw_read_part (regcache, reg, 0, 4, buf);
+	target += extract_unsigned_integer (buf, 4, byte_order) & -4;
+      }
 
       target = target & lslr;
       if (target != next_pc)