From patchwork Sun Nov 26 16:24:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Weigand X-Patchwork-Id: 24536 Received: (qmail 101927 invoked by alias); 26 Nov 2017 16:24:49 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 101596 invoked by uid 89); 26 Nov 2017 16:24:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-27.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1822 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 26 Nov 2017 16:24:47 +0000 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vAQGNmKJ106280 for ; Sun, 26 Nov 2017 11:24:45 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0b-001b2d01.pphosted.com with ESMTP id 2efpvf07tv-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sun, 26 Nov 2017 11:24:45 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Sun, 26 Nov 2017 16:24:41 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vAQGOf4A30146670 for ; Sun, 26 Nov 2017 16:24:41 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 807284C050 for ; Sun, 26 Nov 2017 16:19:41 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6CE3B4C04E for ; Sun, 26 Nov 2017 16:19:41 +0000 (GMT) Received: from oc3748833570.ibm.com (unknown [9.164.156.220]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP for ; Sun, 26 Nov 2017 16:19:41 +0000 (GMT) Received: by oc3748833570.ibm.com (Postfix, from userid 1000) id D0A5FD802F9; Sun, 26 Nov 2017 17:24:40 +0100 (CET) Subject: [spu] Fix single-stepping regression To: gdb-patches@sourceware.org Date: Sun, 26 Nov 2017 17:24:40 +0100 (CET) From: "Ulrich Weigand" MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17112616-0016-0000-0000-00000505AA8E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17112616-0017-0000-0000-00002841875C Message-Id: <20171126162440.D0A5FD802F9@oc3748833570.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-26_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1711260230 Hello, switching spu_software_single_step to use a regcache instead of a frame: https://sourceware.org/ml/gdb-patches/2016-11/msg00355.html caused a serious regression to SPU single-stepping. There were two separate problems: - SPU_LSLR_REGNUM is a pseudo register, so we must use the "cooked" regcache methods instead of the "raw" ones to access it. - When accessing a branch target register, we must only use the first four bytes of the 16-byte vector register. This was done automatically by the frame routines, but not by the regcache routines. Bye, Ulrich gdb/ChangeLog: 2017-11-26 Ulrich Weigand * spu-tdep.c (spu_software_single_step): Access SPU_LSLR_REGNUM as "cooked" register. Access only first four bytes of branch target registers. diff --git a/gdb/spu-tdep.c b/gdb/spu-tdep.c index ecdc7fc..34a536a 100644 --- a/gdb/spu-tdep.c +++ b/gdb/spu-tdep.c @@ -1632,8 +1632,8 @@ spu_software_single_step (struct regcache *regcache) insn = extract_unsigned_integer (buf, 4, byte_order); /* Get local store limit. */ - lslr = regcache_raw_get_unsigned (regcache, SPU_LSLR_REGNUM); - if (!lslr) + if ((regcache_cooked_read_unsigned (regcache, SPU_LSLR_REGNUM, &lslr) + != REG_VALID) || !lslr) lslr = (ULONGEST) -1; /* Next sequential instruction is at PC + 4, except if the current @@ -1653,7 +1653,10 @@ spu_software_single_step (struct regcache *regcache) if (reg == SPU_PC_REGNUM) target += SPUADDR_ADDR (pc); else if (reg != -1) - target += regcache_raw_get_unsigned (regcache, reg) & -4; + { + regcache_raw_read_part (regcache, reg, 0, 4, buf); + target += extract_unsigned_integer (buf, 4, byte_order) & -4; + } target = target & lslr; if (target != next_pc)