diff mbox series

sim: riscv: Fix some compatiblity issues with gcc

Message ID AS8P193MB1285AFC544FD952E4ECA2577E4032@AS8P193MB1285.EURP193.PROD.OUTLOOK.COM
State New
Headers
Series sim: riscv: Fix some compatiblity issues with gcc |

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Commit Message

Bernd Edlinger April 5, 2024, 7:51 a.m. UTC 
  This makes the riscv simulator able to execute a simple
"hello world" program when gcc is configured
with:

../configure --target=riscv-none-elf

The first problem is that gcc generates rv32
code by default in this configuration, while
riscv64-none-elf generates rv64 code by default.

So change the riscv/acinclude.m4 to use the same
logic here.

And the second issue is that gcc does by default
generate instructions in INSN_CLASS_C, so move
the M(GC) to top of list, in riscv/model_list.def.

Then there was apparently a confusion which cpu
model uses JAL and which ADDIW.  Fixed that in
execute_c, case MATCH_C_JAL | MATCH_C_ADDIW.

With these changes a simple c-prgram can be executed,
however there is still work to do, since when the
program does floating point operations, gcc starts to
generate hardware floating point instructions, with no
obvious opt-out option.

Note the gcc test suite can be used to test the
simulator in this way:

make check-gcc RUNTESTFLAGS="--target_board=multi-sim SIM=riscv-none-elf-run"

Now many tests are passed, except those which use
floating point instructions.

Fixes 3224e32fb84f ("sim: riscv: Add support for compressed integer instructions")
---
 sim/configure            | 6 +++---
 sim/riscv/acinclude.m4   | 4 ++--
 sim/riscv/model_list.def | 2 +-
 sim/riscv/sim-main.c     | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/sim/configure b/sim/configure
index 1ebef377973..fdc0a86d524 100755
--- a/sim/configure
+++ b/sim/configure
@@ -17479,10 +17479,10 @@  $as_echo "$sim_ppc_xor_endian" >&6; }
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking riscv bitsize" >&5
 $as_echo_n "checking riscv bitsize... " >&6; }
-SIM_RISCV_BITSIZE=64
+SIM_RISCV_BITSIZE=32
 case $target in #(
-  riscv32*) :
-    SIM_RISCV_BITSIZE=32 ;; #(
+  riscv64*) :
+    SIM_RISCV_BITSIZE=64 ;; #(
   *) :
      ;;
 esac
diff --git a/sim/riscv/acinclude.m4 b/sim/riscv/acinclude.m4
index 0c6290c9c08..e9953c1017d 100644
--- a/sim/riscv/acinclude.m4
+++ b/sim/riscv/acinclude.m4
@@ -15,8 +15,8 @@  dnl along with this program.  If not, see <http://www.gnu.org/licenses/>.
 dnl
 dnl NB: This file is included in sim/configure, so keep settings namespaced.
 AC_MSG_CHECKING([riscv bitsize])
-SIM_RISCV_BITSIZE=64
+SIM_RISCV_BITSIZE=32
 AS_CASE([$target],
-	[riscv32*], [SIM_RISCV_BITSIZE=32])
+	[riscv64*], [SIM_RISCV_BITSIZE=64])
 AC_MSG_RESULT([$SIM_RISCV_BITSIZE])
 AC_SUBST(SIM_RISCV_BITSIZE)
diff --git a/sim/riscv/model_list.def b/sim/riscv/model_list.def
index b83557e5539..df9ec897126 100644
--- a/sim/riscv/model_list.def
+++ b/sim/riscv/model_list.def
@@ -1,9 +1,9 @@ 
+M(GC)
 M(G)
 M(I)
 M(IM)
 M(IMA)
 M(IA)
-M(GC)
 M(IC)
 M(IMC)
 M(IMAC)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index adff99921c6..9c0d070aa60 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1018,7 +1018,7 @@  execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_C_JAL | MATCH_C_ADDIW:
       /* JAL and ADDIW have the same mask but are only available on RV64 or
 	 RV32 respectively.  */
-      if (RISCV_XLEN (cpu) == 64)
+      if (RISCV_XLEN (cpu) == 32)
 	{
 	  imm = EXTRACT_CJTYPE_IMM (iw);
 	  TRACE_INSN (cpu, "c.jal %" PRIxTW,
@@ -1027,7 +1027,7 @@  execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	  pc = riscv_cpu->pc + imm;
 	  TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
 	}
-      else if (RISCV_XLEN (cpu) == 32)
+      else if (RISCV_XLEN (cpu) == 64)
 	{
 	  imm = EXTRACT_CITYPE_IMM (iw);
 	  TRACE_INSN (cpu, "c.addiw %s, %s, %#" PRIxTW ";  // %s += %#" PRIxTW,