diff mbox

[2/4] Fall back to a default value of 0 for the MISA register.

Message ID 20180921092721.GY5952@embecosm.com
State New
Headers show

Commit Message

Andrew Burgess Sept. 21, 2018, 9:27 a.m. UTC
* John Baldwin <jhb@FreeBSD.org> [2018-09-20 16:01:04 -0700]:

> On 9/20/18 2:51 PM, Andrew Burgess wrote:
> > * John Baldwin <jhb@FreeBSD.org> [2018-09-20 13:31:46 -0700]:
> >> @@ -426,7 +420,22 @@ riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
> >>  {
> >>    if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
> >>      {
> >> -      if (riscv_has_feature (gdbarch, 'C'))
> >> +      enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
> > 
> > byte_order is unused.
> 
> Will fix.
> 
> >> +      gdb_byte buf[1];
> >> +      int status;
> >> +
> >> +      /* Read the opcode byte to determine the instruction length.  */
> >> +      status = target_read_memory (*pcptr, buf, 1);
> > 
> > This should use target_read_code.  I know that we already have some
> > (incorrect) uses of target_read_memory in riscv-tdep.c, but we can fix
> > those later.
> 
> Ok.
> 
> > However, this causes a testsuite regression for gdb.gdb/unittest.exp.
> > You can easily reproduce the issue with:
> > 
> >     (gdb) maintenance selftest 
> > 
> > We probably need to add a riscv specific case into
> > disasm-selftest.c:print_one_insn_test, lots of other targets already
> > do.
> 
> Ok.  I'll reproduce that and figure out the fix and include it in a V2
> patch.
> 
> One other question is if I drop the change to default MISA to 0, we should
> perhaps fix the comment above riscv_read_misa?  The comment implies that
> it falls back to zero if it can't read the register and it does that for
> the !target_has_registers case already.  It's not clear from the comment
> that targets are required to provide MISA.

I'm kind-of mixed about the default 0 patch.  The spec says:

    The misa CSR is an XLEN-bit WARL read-write register reporting the
    ISA supported by the hart. This register must be readable in any
    implementation, but a value of zero can be returned to indicate
    the misa register has not been implemented, requiring that CPU
    capabilities be determined through a separate non-standard
    mechanism.

So, it doesn't seem to crazy to say that in GDB, if we make not one,
but two attempts to find a MISA value, fail on both, then we could
assume a default of 0.  After all, the default of 0 just means, go
figure out an answer for yourself, so we shouldn't be any worse off.

Still, it would probably be a good thing if targets did just provide a
0 value for misa on their own as that would be more inline with the
spec (I think).

Having just looked at riscv_read_misa_reg again, it turns out that
it's completely broken anyway.  Take a look at how the READ_P
parameter is initialised in the caller and then (not) set in
function.

Further, the one and only caller, checks READ_P /or/ for a return
value of 0, so just defaulting to 0 would be fine.  At a minimum we
should apply this patch:

## START ##


## END ##

Jim: Given that we agree that targets should definitely provide a
value for misa, at a minimum just returning the constant 0.  But,
given that GDB already defaults to 0 in some cases anyway.  And the
spec is quite clear that 0 is the right default value in the absence
of anything better, would you be OK with a patch that does return a
default of 0?

Thanks,
Andrew

> 
> -- 
> John Baldwin
> 
>

Comments

Jim Wilson Sept. 21, 2018, 5:25 p.m. UTC | #1
On Fri, Sep 21, 2018 at 2:27 AM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> Jim: Given that we agree that targets should definitely provide a
> value for misa, at a minimum just returning the constant 0.  But,
> given that GDB already defaults to 0 in some cases anyway.  And the
> spec is quite clear that 0 is the right default value in the absence
> of anything better, would you be OK with a patch that does return a
> default of 0?

The patch to decode an instruction to decide whether to use a
compressed breakpoint or not solves my main problem.  There is also
the issue of finding FP register size, but since we only support
rv64gc at the moment, it isn't a serious problem.  Also, I think the
linker kernel may already be passing FP info via auxvec/hwcap, so I
think we already have an alternate solution for that which just needs
to be implemented.  I haven't looked at that yet.  So yes, I think it
is OK to start defaulting misa to 0.

FYI I have a qemu patch, which I may someday finish, that adds XML
register support to the RISC-V qemu system-mode port, which allows
qemu to provide a correct value of misa.  We know that misa accesses
already work with embedded targets via OpenOCD.  So it is just linux
and freebsd that need to worry about misa.

The qemu patch is here, though it looks like github is confused by
rebasing and the patch isn't readable anymore.
    https://github.com/riscv/riscv-qemu/pull/160
I'll have to figure out how to fix that.

Jim
John Baldwin Sept. 24, 2018, 8:35 p.m. UTC | #2
On 9/21/18 2:27 AM, Andrew Burgess wrote:
> * John Baldwin <jhb@FreeBSD.org> [2018-09-20 16:01:04 -0700]:
> 
>> On 9/20/18 2:51 PM, Andrew Burgess wrote:
>>> * John Baldwin <jhb@FreeBSD.org> [2018-09-20 13:31:46 -0700]:
>> One other question is if I drop the change to default MISA to 0, we should
>> perhaps fix the comment above riscv_read_misa?  The comment implies that
>> it falls back to zero if it can't read the register and it does that for
>> the !target_has_registers case already.  It's not clear from the comment
>> that targets are required to provide MISA.
> 
> I'm kind-of mixed about the default 0 patch.  The spec says:
> 
>     The misa CSR is an XLEN-bit WARL read-write register reporting the
>     ISA supported by the hart. This register must be readable in any
>     implementation, but a value of zero can be returned to indicate
>     the misa register has not been implemented, requiring that CPU
>     capabilities be determined through a separate non-standard
>     mechanism.
> 
> So, it doesn't seem to crazy to say that in GDB, if we make not one,
> but two attempts to find a MISA value, fail on both, then we could
> assume a default of 0.  After all, the default of 0 just means, go
> figure out an answer for yourself, so we shouldn't be any worse off.
> 
> Still, it would probably be a good thing if targets did just provide a
> 0 value for misa on their own as that would be more inline with the
> spec (I think).
> 
> Having just looked at riscv_read_misa_reg again, it turns out that
> it's completely broken anyway.  Take a look at how the READ_P
> parameter is initialised in the caller and then (not) set in
> function.
> 
> Further, the one and only caller, checks READ_P /or/ for a return
> value of 0, so just defaulting to 0 would be fine.  At a minimum we
> should apply this patch:
> 
> ## START ##
> 
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index 254914c9c7e..52e101e6ab8 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -302,7 +302,7 @@ static unsigned int riscv_debug_unwinder = 0;
>     default (false).  */
>  
>  static uint32_t
> -riscv_read_misa_reg (bool *read_p)
> +riscv_read_misa_reg ()
>  {
>    uint32_t value = 0;
>  
> @@ -334,13 +334,10 @@ riscv_read_misa_reg (bool *read_p)
>  static bool
>  riscv_has_feature (struct gdbarch *gdbarch, char feature)
>  {
> -  bool have_read_misa = false;
> -  uint32_t misa;
> -
>    gdb_assert (feature >= 'A' && feature <= 'Z');
>  
> -  misa = riscv_read_misa_reg (&have_read_misa);
> -  if (!have_read_misa || misa == 0)
> +  uint32_t misa = riscv_read_misa_reg ();
> +  if (misa == 0)
>      misa = gdbarch_tdep (gdbarch)->core_features;
>  
>    return (misa & (1 << (feature - 'A'))) != 0;
> 
> ## END ##
> 
> And, better still would be something more like your original patch:
> 
> ## START ##
> 
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index 254914c9c7e..58e4c221a7c 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -302,7 +302,7 @@ static unsigned int riscv_debug_unwinder = 0;
>     default (false).  */
>  
>  static uint32_t
> -riscv_read_misa_reg (bool *read_p)
> +riscv_read_misa_reg ()
>  {
>    uint32_t value = 0;
>  
> @@ -310,18 +310,23 @@ riscv_read_misa_reg (bool *read_p)
>      {
>        struct frame_info *frame = get_current_frame ();
>  
> -      TRY
> -	{
> -	  value = get_frame_register_unsigned (frame,
> -					       RISCV_CSR_MISA_REGNUM);
> -	}
> -      CATCH (ex, RETURN_MASK_ERROR)
> +      /* Old cores might have MISA located at a different offset.  */
> +      int misa_regs[] =
> +        { RISCV_CSR_MISA_REGNUM, RISCV_CSR_LEGACY_MISA_REGNUM };
> +
> +      for (int i = 0; i < ARRAY_SIZE (misa_regs); ++i)
>  	{
> -	  /* Old cores might have MISA located at a different offset.  */
> -	  value = get_frame_register_unsigned (frame,
> -					       RISCV_CSR_LEGACY_MISA_REGNUM);
> +	  TRY
> +	    {
> +	      value = get_frame_register_unsigned (frame, misa_regs[i]);
> +	      break;
> +	    }
> +	  CATCH (ex, RETURN_MASK_ERROR)
> +	    {
> +	      /* Ignore the error.  */
> +	    }
> +	  END_CATCH
>  	}
> -      END_CATCH
>      }
>  
>    return value;
> @@ -334,13 +339,10 @@ riscv_read_misa_reg (bool *read_p)
>  static bool
>  riscv_has_feature (struct gdbarch *gdbarch, char feature)
>  {
> -  bool have_read_misa = false;
> -  uint32_t misa;
> -
>    gdb_assert (feature >= 'A' && feature <= 'Z');
>  
> -  misa = riscv_read_misa_reg (&have_read_misa);
> -  if (!have_read_misa || misa == 0)
> +  uint32_t misa = riscv_read_misa_reg ();
> +  if (misa == 0)
>      misa = gdbarch_tdep (gdbarch)->core_features;
>  
>    return (misa & (1 << (feature - 'A'))) != 0;
> 
> ## END ##
> 
> Jim: Given that we agree that targets should definitely provide a
> value for misa, at a minimum just returning the constant 0.  But,
> given that GDB already defaults to 0 in some cases anyway.  And the
> spec is quite clear that 0 is the right default value in the absence
> of anything better, would you be OK with a patch that does return a
> default of 0?

FWIW, I think the second patch looks fine.  I can confirm that the breakpoint
patch is sufficient for my limited testing on FreeBSD that I no longer need
the MISA patch so I've dropped it from my local series (I'll post a V2 in a
bit).
Andrew Burgess Sept. 28, 2018, 9:43 a.m. UTC | #3
* Jim Wilson <jimw@sifive.com> [2018-09-21 10:25:47 -0700]:

> On Fri, Sep 21, 2018 at 2:27 AM Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > Jim: Given that we agree that targets should definitely provide a
> > value for misa, at a minimum just returning the constant 0.  But,
> > given that GDB already defaults to 0 in some cases anyway.  And the
> > spec is quite clear that 0 is the right default value in the absence
> > of anything better, would you be OK with a patch that does return a
> > default of 0?
> 
> The patch to decode an instruction to decide whether to use a
> compressed breakpoint or not solves my main problem.  There is also
> the issue of finding FP register size, but since we only support
> rv64gc at the moment, it isn't a serious problem.

I regularly test embeded RiscV against:

  rv32im  rv32imc  rv32imf   rv32imfc

  rv64im  rv64imc  rv64imfd  rv64imfdc

with the last one of those being closes to rv64gc.  The pass rate is
broadly the same against all of these targets, so right now I consider
these equally supported for baremetal.

I understand Linux support might be different.

Thanks,

Andrew


>                                                    Also, I think the
> linker kernel may already be passing FP info via auxvec/hwcap, so I
> think we already have an alternate solution for that which just needs
> to be implemented.  I haven't looked at that yet.  So yes, I think it
> is OK to start defaulting misa to 0.
> 
> FYI I have a qemu patch, which I may someday finish, that adds XML
> register support to the RISC-V qemu system-mode port, which allows
> qemu to provide a correct value of misa.  We know that misa accesses
> already work with embedded targets via OpenOCD.  So it is just linux
> and freebsd that need to worry about misa.
> 
> The qemu patch is here, though it looks like github is confused by
> rebasing and the patch isn't readable anymore.
>     https://github.com/riscv/riscv-qemu/pull/160
> I'll have to figure out how to fix that.
> 
> Jim
Palmer Dabbelt Sept. 28, 2018, 6:25 p.m. UTC | #4
On Fri, 28 Sep 2018 02:43:55 PDT (-0700), andrew.burgess@embecosm.com wrote:
> * Jim Wilson <jimw@sifive.com> [2018-09-21 10:25:47 -0700]:
>
>> On Fri, Sep 21, 2018 at 2:27 AM Andrew Burgess
>> <andrew.burgess@embecosm.com> wrote:
>> > Jim: Given that we agree that targets should definitely provide a
>> > value for misa, at a minimum just returning the constant 0.  But,
>> > given that GDB already defaults to 0 in some cases anyway.  And the
>> > spec is quite clear that 0 is the right default value in the absence
>> > of anything better, would you be OK with a patch that does return a
>> > default of 0?
>>
>> The patch to decode an instruction to decide whether to use a
>> compressed breakpoint or not solves my main problem.  There is also
>> the issue of finding FP register size, but since we only support
>> rv64gc at the moment, it isn't a serious problem.
>
> I regularly test embeded RiscV against:
>
>   rv32im  rv32imc  rv32imf   rv32imfc
>
>   rv64im  rv64imc  rv64imfd  rv64imfdc
>
> with the last one of those being closes to rv64gc.  The pass rate is
> broadly the same against all of these targets, so right now I consider
> these equally supported for baremetal.

For those uniniated in RISC-V, "rv64gc" is the same as "rv64imafdc" (the G is 
short for IMAFD).  Importantly it's probably close enough for embedded GDB 
testing, as all you're missing is the A extension and GDB doesn't really care 
about atomics.

> I understand Linux support might be different.

Right now all that's really supported in Linux land is rv64gc.  The kernel 
should also build on rv64imac, rv32gc, and rv32imac but they're much less 
mature.  The upstream glibc port supports rv64gc and rv64imac, but we test 
those only on rv64gc kernels.

We try our best to avoid breaking the other targets, but until we get some 
better CI up and running I'd expect that non-rv64gc targets do keep falling 
apart.  We're working on it :)

On Linux you should be able to look at the HWCAP in the auxvec, which is meant 
to tell you what user state is available.  The code to fill this out is here

    https://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git/tree/arch/riscv/kernel/cpufeature.c#n26

>
> Thanks,
>
> Andrew
>
>
>>                                                    Also, I think the
>> linker kernel may already be passing FP info via auxvec/hwcap, so I
>> think we already have an alternate solution for that which just needs
>> to be implemented.  I haven't looked at that yet.  So yes, I think it
>> is OK to start defaulting misa to 0.
>>
>> FYI I have a qemu patch, which I may someday finish, that adds XML
>> register support to the RISC-V qemu system-mode port, which allows
>> qemu to provide a correct value of misa.  We know that misa accesses
>> already work with embedded targets via OpenOCD.  So it is just linux
>> and freebsd that need to worry about misa.
>>
>> The qemu patch is here, though it looks like github is confused by
>> rebasing and the patch isn't readable anymore.
>>     https://github.com/riscv/riscv-qemu/pull/160
>> I'll have to figure out how to fix that.
>>
>> Jim
diff mbox

Patch

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 254914c9c7e..52e101e6ab8 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -302,7 +302,7 @@  static unsigned int riscv_debug_unwinder = 0;
    default (false).  */
 
 static uint32_t
-riscv_read_misa_reg (bool *read_p)
+riscv_read_misa_reg ()
 {
   uint32_t value = 0;
 
@@ -334,13 +334,10 @@  riscv_read_misa_reg (bool *read_p)
 static bool
 riscv_has_feature (struct gdbarch *gdbarch, char feature)
 {
-  bool have_read_misa = false;
-  uint32_t misa;
-
   gdb_assert (feature >= 'A' && feature <= 'Z');
 
-  misa = riscv_read_misa_reg (&have_read_misa);
-  if (!have_read_misa || misa == 0)
+  uint32_t misa = riscv_read_misa_reg ();
+  if (misa == 0)
     misa = gdbarch_tdep (gdbarch)->core_features;
 
   return (misa & (1 << (feature - 'A'))) != 0;

## END ##

And, better still would be something more like your original patch:

## START ##

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 254914c9c7e..58e4c221a7c 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -302,7 +302,7 @@  static unsigned int riscv_debug_unwinder = 0;
    default (false).  */
 
 static uint32_t
-riscv_read_misa_reg (bool *read_p)
+riscv_read_misa_reg ()
 {
   uint32_t value = 0;
 
@@ -310,18 +310,23 @@  riscv_read_misa_reg (bool *read_p)
     {
       struct frame_info *frame = get_current_frame ();
 
-      TRY
-	{
-	  value = get_frame_register_unsigned (frame,
-					       RISCV_CSR_MISA_REGNUM);
-	}
-      CATCH (ex, RETURN_MASK_ERROR)
+      /* Old cores might have MISA located at a different offset.  */
+      int misa_regs[] =
+        { RISCV_CSR_MISA_REGNUM, RISCV_CSR_LEGACY_MISA_REGNUM };
+
+      for (int i = 0; i < ARRAY_SIZE (misa_regs); ++i)
 	{
-	  /* Old cores might have MISA located at a different offset.  */
-	  value = get_frame_register_unsigned (frame,
-					       RISCV_CSR_LEGACY_MISA_REGNUM);
+	  TRY
+	    {
+	      value = get_frame_register_unsigned (frame, misa_regs[i]);
+	      break;
+	    }
+	  CATCH (ex, RETURN_MASK_ERROR)
+	    {
+	      /* Ignore the error.  */
+	    }
+	  END_CATCH
 	}
-      END_CATCH
     }
 
   return value;
@@ -334,13 +339,10 @@  riscv_read_misa_reg (bool *read_p)
 static bool
 riscv_has_feature (struct gdbarch *gdbarch, char feature)
 {
-  bool have_read_misa = false;
-  uint32_t misa;
-
   gdb_assert (feature >= 'A' && feature <= 'Z');
 
-  misa = riscv_read_misa_reg (&have_read_misa);
-  if (!have_read_misa || misa == 0)
+  uint32_t misa = riscv_read_misa_reg ();
+  if (misa == 0)
     misa = gdbarch_tdep (gdbarch)->core_features;
 
   return (misa & (1 << (feature - 'A'))) != 0;