[00/11] sim: riscv: simulation of single and double precision floating point instructions
Message ID | 20240226142234.1628932-1-bhushan.attarde@imgtec.com |
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Headers |
Return-Path: <gdb-patches-bounces+patchwork=sourceware.org@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C629C38582A3 for <patchwork@sourceware.org>; Mon, 26 Feb 2024 14:24:45 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) by sourceware.org (Postfix) with ESMTPS id E18F73858421 for <gdb-patches@sourceware.org>; Mon, 26 Feb 2024 14:23:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E18F73858421 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=imgtec.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E18F73858421 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957385; cv=none; b=oUo4LCofN8rknqR2mLbJgvHaaBZtEtYMlOVseLaVKxB8Xe8VNaiFjE//ykQBrRFVg/7f9tMRm1tAocAOlQ7rAwelGEqs6ukHUA/JFgBoCZZKBcdCfwYdhr8NjJ1DtovJ7dfTayW2fLbB6tRq+Ifnv0Yf1ry2QaH7693Kd3mMhL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957385; c=relaxed/simple; bh=OSIPRMwn1qQxahxMKhZM5oWNp2OkBew3Xg3zjcTwPN4=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=kTCxQLIQwFezLOONBBpKUut7QqigAuHh0iYIvXw/3vE6y+lcMKywHw8Psd/NM0OngQX0DlqGgK9AsvShB+J0z3b8q62kD41ygjwDnMuRaAAf2HZU8o9sAWV+VDnhTcFDCeBUUEMFYFgUAChq58nYynCSNg4ZMl4C8GDTdC0N9EA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q8CPdH013671; Mon, 26 Feb 2024 14:22:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=dk201812; bh=eGFlfZrg r64Ycw2ngA8FYgYBo/ApKd0yjRL6wHGdXIY=; b=PNGOvTjHDJ1VEF+1F8zSDVg8 shMZZ5u2duOmRghHF6ez10GGXIqWyyEsPAJ5H0lyo4UpL79MQls8gabpj3m1OJkM kYcoMY0FDyiNTE4MIoI09/z8Xtn5PLwc5TKUBn5RA6VZzasFT4G9L9m8BwrpVlW6 hgzFs6Fh2YCXI1xDmnIb1pcZsnBwfJZQvBf1v7oCvn3SRc7MWDRrXKlmgl7QI4bh S719R1nRSglG2RrCwryNNSyE0rYGRiJz4KSxV5Qur8/WyyD50rovk3SM1GrnCsbx kblXfxCNudXeME9mp2tE8uYOAF3KuF5AS5FGN2Qq9qRo1k3xcoiqLR3eMkTt5A== Received: from hhmail05.hh.imgtec.org ([217.156.249.195]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 3wf7kssr3e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 26 Feb 2024 14:22:49 +0000 (GMT) Received: from hhbattarde.hh.imgtec.org (10.100.136.78) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 26 Feb 2024 14:22:48 +0000 From: <bhushan.attarde@imgtec.com> To: <gdb-patches@sourceware.org> CC: <aburgess@redhat.com>, <vapier@gentoo.org>, <Jaydeep.Patil@imgtec.com>, Bhushan Attarde <bhushan.attarde@imgtec.com> Subject: [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions Date: Mon, 26 Feb 2024 14:22:23 +0000 Message-ID: <20240226142234.1628932-1-bhushan.attarde@imgtec.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.100.136.78] X-ClientProxiedBy: HHMAIL05.hh.imgtec.org (10.100.10.120) To HHMAIL05.hh.imgtec.org (10.100.10.120) X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: 2VgfUUOb46fRePDDQpf9PNFBSu1l2oRa X-Proofpoint-ORIG-GUID: 2VgfUUOb46fRePDDQpf9PNFBSu1l2oRa X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list <gdb-patches.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/gdb-patches>, <mailto:gdb-patches-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/gdb-patches/> List-Post: <mailto:gdb-patches@sourceware.org> List-Help: <mailto:gdb-patches-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/gdb-patches>, <mailto:gdb-patches-request@sourceware.org?subject=subscribe> Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org |
Series |
sim: riscv: simulation of single and double precision floating point instructions
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Message
Bhushan Attarde
Feb. 26, 2024, 2:22 p.m. UTC
From: Bhushan Attarde <bhushan.attarde@imgtec.com>
Hi All,
This patch series (total 11 patches) adds simulation of riscv single and double
precision floating point instructions. This includes load-store, move, compare,
classify, sign injection, min, max, MAC, conversion and basic arithmetic
instructions. Each patch also includes tests for the corresponding instructions.
The tool-chain sources used are from:
https://github.com/riscv-collab/riscv-gnu-toolchain.git
And gdb sources are replaced with latest upstream sources from:
https://sourceware.org/git/binutils-gdb.git
GDB is configured with --target=riscv64-unknown-elf option.
Contributions from:
Bhushan Attarde (Bhushan.Attarde@imgtec.com)
Jaydeep Patil (Jaydeep.Patil@imgtec.com)
Bhushan Attarde (11):
sim: riscv: Add single precision floating-point load-store, move,
compare and classify instructions
sim: riscv: Add single precision floating-point sign injection, min
and max instructions
sim: riscv: Add floating-point CSR instructions
sim: riscv: Add single precision floating-point MAC instructions
sim: riscv: Add single precision floating-point basic arithmetic
instructions
sim: riscv: Add single-precision floating-point conversion
instructions
sim: riscv: Add double precision floating-point load-store, move,
compare and classify instructions
sim: riscv: Add double precision floating-point sign-injection, min
and max instructions
sim: riscv: Add double precision floating-point MAC instructions
sim: riscv: Add double precision floating-point basic arithmetic
instructions
sim: riscv: Add double precision floating-point conversion
instructions
sim/riscv/model_list.def | 4 +
sim/riscv/sim-main.c | 1544 ++++++++++++++++++++++++
sim/testsuite/riscv/d-basic-arith.s | 128 ++
sim/testsuite/riscv/d-conversion.s | 111 ++
sim/testsuite/riscv/d-fp-compare.s | 94 ++
sim/testsuite/riscv/d-fp-load-store.s | 58 +
sim/testsuite/riscv/d-fp-sign-inject.s | 87 ++
sim/testsuite/riscv/f-csr.s | 56 +
sim/testsuite/riscv/s-basic-arith.s | 131 ++
sim/testsuite/riscv/s-conversion-l.s | 60 +
sim/testsuite/riscv/s-conversion.s | 61 +
sim/testsuite/riscv/s-fp-compare.s | 97 ++
sim/testsuite/riscv/s-fp-load-store.s | 62 +
sim/testsuite/riscv/s-fp-sign-inject.s | 90 ++
14 files changed, 2583 insertions(+)
create mode 100644 sim/testsuite/riscv/d-basic-arith.s
create mode 100755 sim/testsuite/riscv/d-conversion.s
create mode 100755 sim/testsuite/riscv/d-fp-compare.s
create mode 100755 sim/testsuite/riscv/d-fp-load-store.s
create mode 100644 sim/testsuite/riscv/d-fp-sign-inject.s
create mode 100644 sim/testsuite/riscv/f-csr.s
create mode 100644 sim/testsuite/riscv/s-basic-arith.s
create mode 100644 sim/testsuite/riscv/s-conversion-l.s
create mode 100644 sim/testsuite/riscv/s-conversion.s
create mode 100644 sim/testsuite/riscv/s-fp-compare.s
create mode 100644 sim/testsuite/riscv/s-fp-load-store.s
create mode 100644 sim/testsuite/riscv/s-fp-sign-inject.s
Comments
Hi Andrew/Mike, Could you please find some time to review this patch? Thank you, Bhushan -----Original Message----- From: Bhushan Attarde <Bhushan.Attarde@imgtec.com> Sent: Monday, February 26, 2024 7:52 PM To: gdb-patches@sourceware.org Cc: aburgess@redhat.com; vapier@gentoo.org; Jaydeep Patil <Jaydeep.Patil@imgtec.com>; Bhushan Attarde <Bhushan.Attarde@imgtec.com> Subject: [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions *** NOTE: This is an internal email from Imagination Technologies *** From: Bhushan Attarde <bhushan.attarde@imgtec.com> Hi All, This patch series (total 11 patches) adds simulation of riscv single and double precision floating point instructions. This includes load-store, move, compare, classify, sign injection, min, max, MAC, conversion and basic arithmetic instructions. Each patch also includes tests for the corresponding instructions. The tool-chain sources used are from: https://github.com/riscv-collab/riscv-gnu-toolchain.git And gdb sources are replaced with latest upstream sources from: https://sourceware.org/git/binutils-gdb.git GDB is configured with --target=riscv64-unknown-elf option. Contributions from: Bhushan Attarde (Bhushan.Attarde@imgtec.com) Jaydeep Patil (Jaydeep.Patil@imgtec.com) Bhushan Attarde (11): sim: riscv: Add single precision floating-point load-store, move, compare and classify instructions sim: riscv: Add single precision floating-point sign injection, min and max instructions sim: riscv: Add floating-point CSR instructions sim: riscv: Add single precision floating-point MAC instructions sim: riscv: Add single precision floating-point basic arithmetic instructions sim: riscv: Add single-precision floating-point conversion instructions sim: riscv: Add double precision floating-point load-store, move, compare and classify instructions sim: riscv: Add double precision floating-point sign-injection, min and max instructions sim: riscv: Add double precision floating-point MAC instructions sim: riscv: Add double precision floating-point basic arithmetic instructions sim: riscv: Add double precision floating-point conversion instructions sim/riscv/model_list.def | 4 + sim/riscv/sim-main.c | 1544 ++++++++++++++++++++++++ sim/testsuite/riscv/d-basic-arith.s | 128 ++ sim/testsuite/riscv/d-conversion.s | 111 ++ sim/testsuite/riscv/d-fp-compare.s | 94 ++ sim/testsuite/riscv/d-fp-load-store.s | 58 + sim/testsuite/riscv/d-fp-sign-inject.s | 87 ++ sim/testsuite/riscv/f-csr.s | 56 + sim/testsuite/riscv/s-basic-arith.s | 131 ++ sim/testsuite/riscv/s-conversion-l.s | 60 + sim/testsuite/riscv/s-conversion.s | 61 + sim/testsuite/riscv/s-fp-compare.s | 97 ++ sim/testsuite/riscv/s-fp-load-store.s | 62 + sim/testsuite/riscv/s-fp-sign-inject.s | 90 ++ 14 files changed, 2583 insertions(+) create mode 100644 sim/testsuite/riscv/d-basic-arith.s create mode 100755 sim/testsuite/riscv/d-conversion.s create mode 100755 sim/testsuite/riscv/d-fp-compare.s create mode 100755 sim/testsuite/riscv/d-fp-load-store.s create mode 100644 sim/testsuite/riscv/d-fp-sign-inject.s create mode 100644 sim/testsuite/riscv/f-csr.s create mode 100644 sim/testsuite/riscv/s-basic-arith.s create mode 100644 sim/testsuite/riscv/s-conversion-l.s create mode 100644 sim/testsuite/riscv/s-conversion.s create mode 100644 sim/testsuite/riscv/s-fp-compare.s create mode 100644 sim/testsuite/riscv/s-fp-load-store.s create mode 100644 sim/testsuite/riscv/s-fp-sign-inject.s -- 2.25.1
<bhushan.attarde@imgtec.com> writes: > From: Bhushan Attarde <bhushan.attarde@imgtec.com> > > Hi All, > > This patch series (total 11 patches) adds simulation of riscv single > and double I think something went wrong with the threading when you sent these emails, patches 1->3 are threaded together, then the other emails are split into two separate thread blocks: https://inbox.sourceware.org/gdb-patches/20240226142234.1628932-1-bhushan.attarde@imgtec.com/ https://inbox.sourceware.org/gdb-patches/20240226142628.1629048-1-bhushan.attarde@imgtec.com/ https://inbox.sourceware.org/gdb-patches/20240226142845.1629113-1-bhushan.attarde@imgtec.com/ Could you repost them please with the threading fixed, this makes it far easier to apply the complete series, plus keeps all the reviews within a single thread. Thanks, Andrew > precision floating point instructions. This includes load-store, move, compare, > classify, sign injection, min, max, MAC, conversion and basic arithmetic > instructions. Each patch also includes tests for the corresponding instructions. > > The tool-chain sources used are from: > https://github.com/riscv-collab/riscv-gnu-toolchain.git > > And gdb sources are replaced with latest upstream sources from: > https://sourceware.org/git/binutils-gdb.git > > GDB is configured with --target=riscv64-unknown-elf option. > > Contributions from: > Bhushan Attarde (Bhushan.Attarde@imgtec.com) > Jaydeep Patil (Jaydeep.Patil@imgtec.com) > > Bhushan Attarde (11): > sim: riscv: Add single precision floating-point load-store, move, > compare and classify instructions > sim: riscv: Add single precision floating-point sign injection, min > and max instructions > sim: riscv: Add floating-point CSR instructions > sim: riscv: Add single precision floating-point MAC instructions > sim: riscv: Add single precision floating-point basic arithmetic > instructions > sim: riscv: Add single-precision floating-point conversion > instructions > sim: riscv: Add double precision floating-point load-store, move, > compare and classify instructions > sim: riscv: Add double precision floating-point sign-injection, min > and max instructions > sim: riscv: Add double precision floating-point MAC instructions > sim: riscv: Add double precision floating-point basic arithmetic > instructions > sim: riscv: Add double precision floating-point conversion > instructions > > sim/riscv/model_list.def | 4 + > sim/riscv/sim-main.c | 1544 ++++++++++++++++++++++++ > sim/testsuite/riscv/d-basic-arith.s | 128 ++ > sim/testsuite/riscv/d-conversion.s | 111 ++ > sim/testsuite/riscv/d-fp-compare.s | 94 ++ > sim/testsuite/riscv/d-fp-load-store.s | 58 + > sim/testsuite/riscv/d-fp-sign-inject.s | 87 ++ > sim/testsuite/riscv/f-csr.s | 56 + > sim/testsuite/riscv/s-basic-arith.s | 131 ++ > sim/testsuite/riscv/s-conversion-l.s | 60 + > sim/testsuite/riscv/s-conversion.s | 61 + > sim/testsuite/riscv/s-fp-compare.s | 97 ++ > sim/testsuite/riscv/s-fp-load-store.s | 62 + > sim/testsuite/riscv/s-fp-sign-inject.s | 90 ++ > 14 files changed, 2583 insertions(+) > create mode 100644 sim/testsuite/riscv/d-basic-arith.s > create mode 100755 sim/testsuite/riscv/d-conversion.s > create mode 100755 sim/testsuite/riscv/d-fp-compare.s > create mode 100755 sim/testsuite/riscv/d-fp-load-store.s > create mode 100644 sim/testsuite/riscv/d-fp-sign-inject.s > create mode 100644 sim/testsuite/riscv/f-csr.s > create mode 100644 sim/testsuite/riscv/s-basic-arith.s > create mode 100644 sim/testsuite/riscv/s-conversion-l.s > create mode 100644 sim/testsuite/riscv/s-conversion.s > create mode 100644 sim/testsuite/riscv/s-fp-compare.s > create mode 100644 sim/testsuite/riscv/s-fp-load-store.s > create mode 100644 sim/testsuite/riscv/s-fp-sign-inject.s > > -- > 2.25.1