mbox series

[v7,0/1] sim: riscv: Compressed instruction simulation

Message ID 20240123055038.249677-1-jaydeep.patil@imgtec.com
Headers
Series sim: riscv: Compressed instruction simulation |

Message

Jaydeep Patil Jan. 23, 2024, 5:50 a.m. UTC 
  From: Jaydeep Patil <jaydeep.patil@imgtec.com>

Hi Mike, Andrew,

Addressed review comments.
 - Retain the error block which checks length of opcode
 - Change simulator tests to match 'riscv32 riscv64' instead of 'all'

Jaydeep Patil (1):
  sim: riscv: Add support for compressed integer instructions

 sim/riscv/model_list.def        |   9 +
 sim/riscv/sim-main.c            | 332 +++++++++++++++++++++++++++++++-
 sim/testsuite/riscv/allinsn.exp |   2 +-
 sim/testsuite/riscv/c-ext.s     |  95 +++++++++
 sim/testsuite/riscv/jalr.s      |   2 +-
 sim/testsuite/riscv/m-ext.s     |   2 +-
 sim/testsuite/riscv/pass.s      |   2 +-
 7 files changed, 436 insertions(+), 8 deletions(-)
 create mode 100644 sim/testsuite/riscv/c-ext.s