[v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks.

  Hi,

Changes from v1:
 - Revamped the target selectors again.
 - Fixed some syntax as well as caching errors that were still present.
 - Adjusted some test cases I missed.

The current situation with target selectors is improvable at best.
We definitely need to discern between being able to build a
test with the current configuration and running the test on the
current target which this patch attempts to do.  There might
be a need for more fine-grained checks in the future that could
also go into our target-specific riscv.exp in the subdirectories
but for now I think we're good.

A bit more detail is in the patch description below.  The testsuite
is as clean as before for the configurations I tried: default, rv64gcv,
rv64gcv_zfhmin, rv64gc, rv64gc_zfh, rv64gc_zfhmin.  I hope I didn't
overlook tests that appear unsupported now but shouldn't be.

@Pan: No need to check the old version anymore, thanks.  This patch
is preferred.

Regards
 Robin

This introduces new checks for run tests.  Currently we have
riscv_vector as well as rv32 and rv64 which all check if GCC (with the
current configuration) can build the respective tests.

Many tests specify e.g. a different -march for vector which
makes the check fail even though we could build as well as run
those tests.

vector_hw now tries to compile, link and execute a simple vector example
file.  If this succeeds the respective test can run.

Similarly we introduce a zvfh_hw check which will be used in the
upcoming floating-point unop/binop tests as well as rv32_hw and
rv64_hw checks that are currently unused.

To conclude:
 - If we want a testcase to only compile when the current configuration
   has vector support we use {riscv_vector}.
 - If we want a testcase to run when the current target can supports
   executing vector instructions we use {riscv_vector_hw}.
   It still needs to be ensured that we can actually build the test
   which can be achieved by either
   (1) compiling with e.g. -march=rv64gcv or
   (2) only enabling the test when the current configuration supports
     vector via {riscsv_vector}.

The same principle applies for zfh, zfhmin and zvfh but we do not yet
have all target selectors.  In the meanwhile we need to make sure to
specify the proper -march flags like in (1).

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/shift-run.c: Use
	riscv_vector_hw.
	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Dito.
	* gcc.target/riscv/rvv/autovec/series_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/unop/abs-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Use.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Use.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Use.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Use.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Use.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Use.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Use.
	* g++.target/riscv/rvv/base/bug-10.C: Use.
	* g++.target/riscv/rvv/base/bug-11.C: Use.
	* g++.target/riscv/rvv/base/bug-12.C: Use.
	* g++.target/riscv/rvv/base/bug-13.C: Use.
	* g++.target/riscv/rvv/base/bug-14.C: Use.
	* g++.target/riscv/rvv/base/bug-15.C: Use.
	* g++.target/riscv/rvv/base/bug-16.C: Use.
	* g++.target/riscv/rvv/base/bug-17.C: Use.
	* g++.target/riscv/rvv/base/bug-2.C: Use.
	* g++.target/riscv/rvv/base/bug-23.C: Use.
	* g++.target/riscv/rvv/base/bug-3.C: Use.
	* g++.target/riscv/rvv/base/bug-4.C: Use.
	* g++.target/riscv/rvv/base/bug-5.C: Use.
	* g++.target/riscv/rvv/base/bug-6.C: Use.
	* g++.target/riscv/rvv/base/bug-7.C: Use.
	* g++.target/riscv/rvv/base/bug-8.C: Use.
	* g++.target/riscv/rvv/base/bug-9.C: Use.
	* lib/target-supports.exp: Add riscv_vect_hw, rv32_hw, rv64_hw
	and zfh_hw, zfhmin_hw, zvfh_hw checks.
---
 .../g++.target/riscv/rvv/base/bug-10.C        |   2 +-
 .../g++.target/riscv/rvv/base/bug-11.C        |   2 +-
 .../g++.target/riscv/rvv/base/bug-12.C        |   2 +-
 .../g++.target/riscv/rvv/base/bug-13.C        |   2 +-
 .../g++.target/riscv/rvv/base/bug-14.C        |   2 +-
 .../g++.target/riscv/rvv/base/bug-15.C        |   2 +-
 .../g++.target/riscv/rvv/base/bug-16.C        |   2 +-
 .../g++.target/riscv/rvv/base/bug-17.C        |   2 +-
 .../g++.target/riscv/rvv/base/bug-2.C         |   2 +-
 .../g++.target/riscv/rvv/base/bug-23.C        |   2 +-
 .../g++.target/riscv/rvv/base/bug-3.C         |   2 +-
 .../g++.target/riscv/rvv/base/bug-4.C         |   2 +-
 .../g++.target/riscv/rvv/base/bug-5.C         |   2 +-
 .../g++.target/riscv/rvv/base/bug-6.C         |   2 +-
 .../g++.target/riscv/rvv/base/bug-7.C         |   2 +-
 .../g++.target/riscv/rvv/base/bug-8.C         |   2 +-
 .../g++.target/riscv/rvv/base/bug-9.C         |   2 +-
 .../riscv/rvv/autovec/binop/shift-run.c       |   2 +-
 .../rvv/autovec/binop/shift-scalar-run.c      |   2 +-
 .../riscv/rvv/autovec/binop/vadd-run.c        |   2 +-
 .../riscv/rvv/autovec/binop/vand-run.c        |   2 +-
 .../riscv/rvv/autovec/binop/vdiv-run.c        |   2 +-
 .../riscv/rvv/autovec/binop/vmax-run.c        |   2 +-
 .../riscv/rvv/autovec/binop/vmin-run.c        |   2 +-
 .../riscv/rvv/autovec/binop/vmul-run.c        |   2 +-
 .../riscv/rvv/autovec/binop/vor-run.c         |   2 +-
 .../riscv/rvv/autovec/binop/vrem-run.c        |   2 +-
 .../riscv/rvv/autovec/binop/vsub-run.c        |   2 +-
 .../riscv/rvv/autovec/binop/vxor-run.c        |   2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-1.c       |   2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-2.c       |   2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-3.c       |   2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-4.c       |   2 +-
 .../rvv/autovec/conversions/vfcvt_rtz-run.c   |   2 +-
 .../riscv/rvv/autovec/conversions/vncvt-run.c |   2 +-
 .../riscv/rvv/autovec/conversions/vsext-run.c |   2 +-
 .../riscv/rvv/autovec/conversions/vzext-run.c |   2 +-
 .../autovec/partial/multiple_rgroup_run-1.c   |   2 +-
 .../autovec/partial/multiple_rgroup_run-2.c   |   2 +-
 .../autovec/partial/multiple_rgroup_run-3.c   |   2 +-
 .../autovec/partial/multiple_rgroup_run-4.c   |   2 +-
 .../rvv/autovec/partial/single_rgroup_run-1.c |   2 +-
 .../riscv/rvv/autovec/partial/slp_run-1.c     |   2 +-
 .../riscv/rvv/autovec/partial/slp_run-2.c     |   2 +-
 .../riscv/rvv/autovec/partial/slp_run-3.c     |   2 +-
 .../riscv/rvv/autovec/partial/slp_run-4.c     |   2 +-
 .../riscv/rvv/autovec/partial/slp_run-5.c     |   2 +-
 .../riscv/rvv/autovec/partial/slp_run-6.c     |   2 +-
 .../riscv/rvv/autovec/partial/slp_run-7.c     |   2 +-
 .../riscv/rvv/autovec/series_run-1.c          |   2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-1.c   |   2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-2.c   |   2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-3.c   |   2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-4.c   |   2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-5.c   |   2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-6.c   |   2 +-
 .../riscv/rvv/autovec/unop/abs-run.c          |   2 +-
 .../riscv/rvv/autovec/unop/vneg-run.c         |   2 +-
 .../riscv/rvv/autovec/unop/vnot-run.c         |   2 +-
 .../vls-vlmax/init-repeat-sequence-run-1.c    |   2 +-
 .../vls-vlmax/init-repeat-sequence-run-2.c    |   2 +-
 .../vls-vlmax/init-repeat-sequence-run-3.c    |   2 +-
 .../rvv/autovec/vls-vlmax/insert_run-1.c      |   2 +-
 .../rvv/autovec/vls-vlmax/insert_run-2.c      |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-1.c |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-2.c |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-3.c |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-4.c |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-5.c |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-6.c |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-7.c |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-1.c  |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-2.c  |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-3.c  |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-4.c  |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-5.c  |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-6.c  |   2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-7.c  |   2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-1.c      |   2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-2.c      |   2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-3.c      |   2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-4.c      |   2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-5.c      |   2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-6.c      |   2 +-
 .../riscv/rvv/autovec/vmv-imm-run.c           |   2 +-
 .../riscv/rvv/autovec/widen/widen_run-1.c     |   2 +-
 .../riscv/rvv/autovec/widen/widen_run-2.c     |   2 +-
 .../riscv/rvv/autovec/widen/widen_run-3.c     |   2 +-
 .../riscv/rvv/autovec/widen/widen_run-4.c     |   2 +-
 .../riscv/rvv/autovec/widen/widen_run-5.c     |   2 +-
 .../riscv/rvv/autovec/widen/widen_run-6.c     |   2 +-
 .../riscv/rvv/autovec/widen/widen_run-7.c     |   2 +-
 .../riscv/rvv/autovec/widen/widen_run-8.c     |   2 +-
 .../riscv/rvv/autovec/widen/widen_run-9.c     |   2 +-
 gcc/testsuite/lib/target-supports.exp         | 128 ++++++++++++++++++
 95 files changed, 222 insertions(+), 94 deletions(-)

Message ID	b834b2f5-e505-71be-c694-bbf529ec6bd4@gmail.com
State	Dropped
Headers	Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8776D3857400 for <patchwork@sourceware.org>; Thu, 15 Jun 2023 15:07:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8776D3857400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686841639; bh=mCeLoavtP/cSmuTgEkvb18YrLi5btn4CnSrOsNPmVV8=; h=Date:Cc:To:References:Subject:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=wwZP3mSQMppcOjI/5oj37INT5zJEJGYBz+WbEva8/lJ7aTH/1UpFtTRoWfn8lNudi oBZvinFN0C9+F/Ny2Qt3ZkpTdY+erNWR7UaoeFNNY+ijHMnfygBsf8pEf0ZT6fou8x UY2Cqf0VVJ43bIBQTz0Srg94/0PI0lQ7j0YkfB9k= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id 9FE7A3858C2F for <gcc-patches@gcc.gnu.org>; Thu, 15 Jun 2023 15:06:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9FE7A3858C2F Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-51873d9a75dso1863344a12.1 for <gcc-patches@gcc.gnu.org>; Thu, 15 Jun 2023 08:06:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686841603; x=1689433603; h=content-transfer-encoding:in-reply-to:subject:from:references:to :content-language:cc:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=mCeLoavtP/cSmuTgEkvb18YrLi5btn4CnSrOsNPmVV8=; b=g6TbAIBW1Jv0cCBnXGuaEUybdEMfvd2qHWHWHzBsERoKGZQBge5NUeFOzYy213Rz5z YWUq85+zEtlILcldYI5o7flpxUxN3bgk82KeXlm3ghdfb+lg73l+NfY5O1kGy6sgh35u SnlVd5h99t3EdXBrPpnKDlhRoSUqgDuznoXP9rJX6ldsAVg/2FN9eVD3/RGH8U27IVR6 udVI/8jvu87vtCmP3/qKum5DgYPENuh0gLSY1SCP/Apk4RxfzoCnama3rItMU1t/gTD1 0bAlIQKr/b3ZgOoqMMTGZZ0bKGylfTlRRCfMoCakQLXB+7Vxn1VPDBgp/+pHp3CqSaTA 5fCQ== X-Gm-Message-State: AC+VfDwt/f5Stc09nKg/P0kAh31C59U0VEQxls4EUTHRPfu2XM/ZOMmH swc1P3Se6IsRBtoBsWE+DeKq1M5DWHw= X-Google-Smtp-Source: ACHHUZ6KEVcqFXONmGW5lL4qKYBB9gr2c254+O9S1Tz2nrQn+8HD/yMnSLOye3IFS4MjmAb/p79u7g== X-Received: by 2002:aa7:c65a:0:b0:51a:2d90:389a with SMTP id z26-20020aa7c65a000000b0051a2d90389amr1337336edr.4.1686841600924; Thu, 15 Jun 2023 08:06:40 -0700 (PDT) Received: from [192.168.1.23] (ip-046-005-130-086.um12.pools.vodafone-ip.de. [46.5.130.86]) by smtp.gmail.com with ESMTPSA id w18-20020aa7dcd2000000b00504ecc4fa96sm8994425edu.95.2023.06.15.08.06.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Jun 2023 08:06:40 -0700 (PDT) Message-ID: <b834b2f5-e505-71be-c694-bbf529ec6bd4@gmail.com> Date: Thu, 15 Jun 2023 17:06:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cc: rdapp.gcc@gmail.com Content-Language: en-US To: gcc-patches <gcc-patches@gcc.gnu.org>, palmer <palmer@dabbelt.com>, Kito Cheng <kito.cheng@gmail.com>, "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>, jeffreyalaw <jeffreyalaw@gmail.com>, vineetg@rivosinc.com, "Li, Pan2" <pan2.li@intel.com> References: <e0f91d40-dea8-e398-9678-6ede777de4f0@gmail.com> Subject: [PATCH v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks. In-Reply-To: <e0f91d40-dea8-e398-9678-6ede777de4f0@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: Robin Dapp via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Robin Dapp <rdapp.gcc@gmail.com> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org>
Series	[v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks. \| [v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks.

Context	Check	Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm	success	Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-aarch64	success	Testing passed
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64	success	Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-arm	success	Testing passed

[v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks.

Checks

Commit Message

Comments

Patch