diff mbox series

aarch64: Fix parens in aarch64_stp_reg_operand [PR113061]

Message ID ZYDHvnz5bi//bzdQ@arm.com
State Committed
Commit 2cd55480857bf310c9be7daea39ea266772d3666
Headers
Series aarch64: Fix parens in aarch64_stp_reg_operand [PR113061] |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-aarch64 success Testing passed

Commit Message

Alex Coplan Dec. 18, 2023, 10:29 p.m. UTC 
  In r14-6603-gfcdd2757c76bf925115b8e1ba4318d6366dd6f09 I messed up the
parentheses in aarch64_stp_reg_operand, the indentation shows the
intended nesting of the conditions.

This patch fixes that.

This fixes PR113061 which shows IRA substituting (const_int 1) into a
writeback stp pattern as a result (and LRA failing to reload the
constant).

Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk?

Thanks,
Alex

gcc/ChangeLog:

	PR target/113061
	* config/aarch64/predicates.md (aarch64_stp_reg_operand): Fix
	parentheses to match intent.

gcc/testsuite/ChangeLog:

	PR target/113061
	* gfortran.dg/PR113061.f90: New test.

Comments

Kyrylo Tkachov Dec. 19, 2023, 8:55 a.m. UTC | #1 
> -----Original Message-----
> From: Alex Coplan <Alex.Coplan@arm.com>
> Sent: Monday, December 18, 2023 10:29 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
> Subject: [PATCH] aarch64: Fix parens in aarch64_stp_reg_operand [PR113061]
> 
> In r14-6603-gfcdd2757c76bf925115b8e1ba4318d6366dd6f09 I messed up the
> parentheses in aarch64_stp_reg_operand, the indentation shows the
> intended nesting of the conditions.
> 
> This patch fixes that.
> 
> This fixes PR113061 which shows IRA substituting (const_int 1) into a
> writeback stp pattern as a result (and LRA failing to reload the
> constant).
> 
> Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk?

Ok.
Thanks,
Kyrill

> 
> Thanks,
> Alex
> 
> gcc/ChangeLog:
> 
> 	PR target/113061
> 	* config/aarch64/predicates.md (aarch64_stp_reg_operand): Fix
> 	parentheses to match intent.
> 
> gcc/testsuite/ChangeLog:
> 
> 	PR target/113061
> 	* gfortran.dg/PR113061.f90: New test.
diff mbox series

Patch

diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 9e6231691c0..510d4d2eaca 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -323,7 +323,7 @@  (define_special_predicate "aarch64_ldp_reg_operand"
 (define_special_predicate "aarch64_stp_reg_operand"
   (ior (match_operand 0 "aarch64_ldp_reg_operand")
        (and (match_code "const_int,const,const_vector,const_double")
-	    (match_test "aarch64_const_zero_rtx_p (op)"))
+	    (match_test "aarch64_const_zero_rtx_p (op)")
 	    (ior
 	      (match_test "GET_MODE (op) == VOIDmode")
 	      (and
@@ -331,7 +331,7 @@  (define_special_predicate "aarch64_stp_reg_operand"
 		(ior
 		  (match_test "mode == VOIDmode")
 		  (match_test "known_eq (GET_MODE_SIZE (mode),
-					 GET_MODE_SIZE (GET_MODE (op)))"))))))
+					 GET_MODE_SIZE (GET_MODE (op)))")))))))
 
 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
 ;; as a 128-bit vec_concat.
diff --git a/gcc/testsuite/gfortran.dg/PR113061.f90 b/gcc/testsuite/gfortran.dg/PR113061.f90
new file mode 100644
index 00000000000..989bc385c76
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/PR113061.f90
@@ -0,0 +1,12 @@ 
+! { dg-do compile }
+! { dg-options "-fno-move-loop-invariants -Oz" }
+module module_foo
+  use iso_c_binding
+  contains
+  subroutine foo(a) bind(c)
+    type(c_ptr)  a(..)
+    select rank(a)
+    end select
+    call bar
+  end
+end