diff mbox series

Fix DImode to TImode sign extend issue, PR target/104868

Message ID YirnIQ1E0C3qlchK@toto.the-meissners.org
State Committed
Commit 3cb27b85a7b977958d53e1a29596ba211d21dde2
Headers
Series Fix DImode to TImode sign extend issue, PR target/104868 |

Commit Message

Michael Meissner March 11, 2022, 6:07 a.m. UTC 
  Fix DImode to TImode sign extend issue, PR target/104898

PR target/104868 had had an issue where my code that updated the DImode to
TImode sign extension for power10 failed.  In looking at the failure
message, the reason is when extendditi2 tries to split the insn, it
generates an insn that does not satisfy its constraints:

	(set (reg:V2DI 65 1)
	     (vec_duplicate:V2DI (reg:DI 0)))

The reason is vsx_splat_v2di does not allow GPR register 0 when the will
be generating a mtvsrdd instruction.  In the definition of the mtvsrdd
instruction, if the RA register is 0, it means clear the upper 64 bits of
the vector instead of moving register GPR 0 to those bits.

When I wrote the extendditi2 pattern, I forgot that mtvsrdd had that
behavior so I used a 'r' constraint instead of 'b'.  In the rare case
where the value is in GPR register 0, this split will fail.

This patch uses the right constraint for extendditi2.

Note, I was unable to get the example to fail.  I built a toolchain, and
modified it so libgfortran was built with -flto.  But I feel confident that
this patch is the right fix for the problem listed in the PR.

Can I check this into the master branch?  Assuming this patch is accepted, I
would incorporate it into the backport for GCC 11.  I wasn't planning on
backporting it to GCC 10, since the original bug (PR target/104698) does not
show up there.

2022-03-10   Michael Meissner  <meissner@linux.ibm.com>

gcc/
	PR target/104868
	* config/rs6000/vsx.md (extendditi2): Use a 'b' constraint when
	moving from a GPR register to an Altivec register.
---
 gcc/config/rs6000/vsx.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Michael Meissner March 11, 2022, 5:07 p.m. UTC | #1 
Matheus Castanho reports that the patch I posted fixes the problem in the
1040868 bug report.
Segher Boessenkool March 11, 2022, 8:41 p.m. UTC | #2 
On Fri, Mar 11, 2022 at 01:07:29AM -0500, Michael Meissner wrote:
> Fix DImode to TImode sign extend issue, PR target/104898

> When I wrote the extendditi2 pattern, I forgot that mtvsrdd had that
> behavior so I used a 'r' constraint instead of 'b'.  In the rare case
> where the value is in GPR register 0, this split will fail.

Note that the machine instructions it would generate would work fine:
mtvsrdd X,0,Y can be used as a "mtvsrld" always.  In fact, generating
such code would be better than mtvsrdd always here.

Do you want to try that?  If not, this is okay for trunk.  Thanks!


Segher
Michael Meissner March 11, 2022, 10:48 p.m. UTC | #3 
On Fri, Mar 11, 2022 at 02:41:05PM -0600, Segher Boessenkool wrote:
> On Fri, Mar 11, 2022 at 01:07:29AM -0500, Michael Meissner wrote:
> > Fix DImode to TImode sign extend issue, PR target/104898
> 
> > When I wrote the extendditi2 pattern, I forgot that mtvsrdd had that
> > behavior so I used a 'r' constraint instead of 'b'.  In the rare case
> > where the value is in GPR register 0, this split will fail.
> 
> Note that the machine instructions it would generate would work fine:
> mtvsrdd X,0,Y can be used as a "mtvsrld" always.  In fact, generating
> such code would be better than mtvsrdd always here.
> 
> Do you want to try that?  If not, this is okay for trunk.  Thanks!

Right now, it will need support (since we don't have a zero_extendditi2 pattern
right now).  I am working on optimizations to do this, but right now it is
simplest just to use "b".
diff mbox series

Patch

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d0fb92f5985..15bd86dfdfb 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5033,7 +5033,7 @@  (define_expand "vsignextend_si_v2di"
 ;; generate the vextsd2q instruction.
 (define_insn_and_split "extendditi2"
   [(set (match_operand:TI 0 "register_operand" "=r,r,v,v,v")
-	(sign_extend:TI (match_operand:DI 1 "input_operand" "r,m,r,wa,Z")))
+	(sign_extend:TI (match_operand:DI 1 "input_operand" "r,m,b,wa,Z")))
    (clobber (reg:DI CA_REGNO))]
   "TARGET_POWERPC64 && TARGET_POWER10"
   "#"