diff mbox series

[v3,02/12] aarch64: Mark x18 register as a fixed register for MS ABI

Message ID VI1PR83MB0431109CC3B6882E4E9812A7F8052@VI1PR83MB0431.EURPRD83.prod.outlook.com
State New
Headers
Series Add aarch64-w64-mingw32 target |

Commit Message

Evgeny Karpov April 11, 2024, 1:48 p.m. UTC 
  From: Zac Walker <zacwalker@microsoft.com>
Date: Thu, 11 Apr 2024 13:30:27 +0200
Subject: [PATCH v3 02/12] aarch64: Mark x18 register as a fixed register for
 MS ABI

Define the MS ABI for aarch64-w64-mingw32.
Adjust FIXED_REGISTERS, CALL_REALLY_USED_REGISTERS and
STATIC_CHAIN_REGNUM for AArch64 MS ABI.
The X18 register is reserved on Windows for the TEB.

gcc/ChangeLog:

	* config.gcc: Define TARGET_AARCH64_MS_ABI when
	AArch64 MS ABI is used.
	* config/aarch64/aarch64.h (FIXED_X18): Adjust
	FIXED_REGISTERS, CALL_REALLY_USED_REGISTERS and
	STATIC_CHAIN_REGNUM for AArch64 MS ABI.
	(CALL_USED_X18): Likewise.
	(FIXED_REGISTERS): Likewise.
	* config/aarch64/aarch64-abi-ms.h: New file.
---
 gcc/config.gcc                      |  1 +
 gcc/config/aarch64/aarch64-abi-ms.h | 34 +++++++++++++++++++++++++++++
 gcc/config/aarch64/aarch64.h        |  7 ++++--
 3 files changed, 40 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/aarch64/aarch64-abi-ms.h
diff mbox series

Patch

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6f97f24af10..0aeb5641461 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -1272,6 +1272,7 @@  aarch64*-*-gnu*)
         tm_defines="${tm_defines}  TARGET_DEFAULT_ASYNC_UNWIND_TABLES=1"
 	;;
 aarch64-*-mingw*)
+	tm_file="${tm_file} aarch64/aarch64-abi-ms.h"
 	tmake_file="${tmake_file} aarch64/t-aarch64"
 	case ${enable_threads} in
 	  "" | yes | win32)
diff --git a/gcc/config/aarch64/aarch64-abi-ms.h b/gcc/config/aarch64/aarch64-abi-ms.h
new file mode 100644
index 00000000000..15dc33d0474
--- /dev/null
+++ b/gcc/config/aarch64/aarch64-abi-ms.h
@@ -0,0 +1,34 @@ 
+/* Machine description for AArch64 MS ABI.
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#ifndef GCC_AARCH64_ABI_MS_H
+#define GCC_AARCH64_ABI_MS_H
+
+/* X18 reserved for the TEB on Windows.  */
+
+#undef FIXED_X18
+#define FIXED_X18 1
+
+#undef CALL_USED_X18
+#define CALL_USED_X18 0
+
+#undef  STATIC_CHAIN_REGNUM
+#define STATIC_CHAIN_REGNUM R17_REGNUM
+
+#endif /* GCC_AARCH64_ABI_MS_H.  */
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 45e901cda64..6d360ca3e33 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -536,11 +536,14 @@  constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
    register.  GCC internally uses the poly_int variable aarch64_sve_vg
    instead.  */
 
+#define FIXED_X18 0
+#define CALL_USED_X18 1
+
 #define FIXED_REGISTERS					\
   {							\
     0, 0, 0, 0,   0, 0, 0, 0,	/* R0 - R7 */		\
     0, 0, 0, 0,   0, 0, 0, 0,	/* R8 - R15 */		\
-    0, 0, 0, 0,   0, 0, 0, 0,	/* R16 - R23 */		\
+    0, 0, FIXED_X18, 0,   0, 0, 0, 0,	/* R16 - R23.  */	\
     0, 0, 0, 0,   0, 1, 0, 1,	/* R24 - R30, SP */	\
     0, 0, 0, 0,   0, 0, 0, 0,   /* V0 - V7 */           \
     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */		\
@@ -564,7 +567,7 @@  constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
   {							\
     1, 1, 1, 1,   1, 1, 1, 1,	/* R0 - R7 */		\
     1, 1, 1, 1,   1, 1, 1, 1,	/* R8 - R15 */		\
-    1, 1, 1, 0,   0, 0, 0, 0,	/* R16 - R23 */		\
+    1, 1, CALL_USED_X18, 0, 0,   0, 0, 0, /* R16 - R23.  */   \
     0, 0, 0, 0,   0, 1, 1, 1,	/* R24 - R30, SP */	\
     1, 1, 1, 1,   1, 1, 1, 1,	/* V0 - V7 */		\
     0, 0, 0, 0,   0, 0, 0, 0,	/* V8 - V15 */		\