diff mbox series

RISC-V: testsuite: Fix reduc-8.c and reduc-9.c

Message ID D7CS8WU05TMQ.2BRFSKCDY5W2Q@gmail.com
State Committed
Commit f7dc4fd62ce4d9287988892b1e94bbdd0ca1c8fa
Headers
Series RISC-V: testsuite: Fix reduc-8.c and reduc-9.c |

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Commit Message

Robin Dapp Jan. 27, 2025, 10:27 a.m. UTC 
  Hi,

in both tests we expect a VEC_SHL_INSERT expression but we now add the
initial value at the end.  Just remove that scan check.

Will commit as obvious after the CI run.

Regards
 Robin


---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c | 1 -
 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c | 1 -
 2 files changed, 2 deletions(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
index fe47aa3648d..518f0c33cc4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
@@ -12,5 +12,4 @@  add_loop (int *x, int n, int res)
   return res;
 }
 
-/* { dg-final { scan-tree-dump-times "VEC_SHL_INSERT" 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vslide1up\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
index 6630d302721..a5bb8dcccb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
@@ -12,5 +12,4 @@  add_loop (float *x, int n, float res)
   return res;
 }
 
-/* { dg-final { scan-tree-dump-times "VEC_SHL_INSERT" 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vfslide1up\.vf\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */