diff mbox series

[committed] i386: psrlq is not used for PERM<a, {0}, 1, 2, 3, 4> [PR113871]

Message ID CAFULd4bewKe-t1nRXkr=RtsoreBhLRa__bUm15+SzzM7Wa5+-Q@mail.gmail.com
State Committed
Commit 15d1dae0d4d1be88d28ad7578a60fd3e36de36d8
Headers
Series [committed] i386: psrlq is not used for PERM<a, {0}, 1, 2, 3, 4> [PR113871] |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm warning Patch is already merged
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 warning Patch is already merged

Commit Message

Uros Bizjak Feb. 27, 2024, 5:44 p.m. UTC 
  Also handle V2BF mode.

    PR target/113871

gcc/ChangeLog:

    * config/i386/mmx.md (V248FI): Add V2BF mode.
    (V24FI_32): Ditto.

gcc/testsuite/ChangeLog:

    * gcc.target/i386/pr113871-5a.c: New test.
    * gcc.target/i386/pr113871-5b.c: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 075309cca9f..2856ae6ffef 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -85,9 +85,9 @@  (define_mode_iterator V2FI [V2SF V2SI])
 
 (define_mode_iterator V24FI [V2SF V2SI V4HF V4HI])
 
-(define_mode_iterator V248FI [V2SF V2SI V4HF V4HI V8QI])
+(define_mode_iterator V248FI [V2SF V2SI V4HF V4BF V4HI V8QI])
 
-(define_mode_iterator V24FI_32 [V2HF V2HI V4QI])
+(define_mode_iterator V24FI_32 [V2HF V2BF V2HI V4QI])
 
 ;; Mapping from integer vector mode to mnemonic suffix
 (define_mode_attr mmxvecsize
diff --git a/gcc/testsuite/gcc.target/i386/pr113871-5a.c b/gcc/testsuite/gcc.target/i386/pr113871-5a.c
new file mode 100644
index 00000000000..25ab82a6eab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr113871-5a.c
@@ -0,0 +1,19 @@ 
+/* PR target/113871 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2" } */
+
+typedef __bf16 vect64 __attribute__((vector_size(8)));
+
+void f (vect64 *a)
+{
+  *a = __builtin_shufflevector(*a, (vect64){0}, 1, 2, 3, 4);
+}
+
+/* { dg-final { scan-assembler "psrlq" } } */
+
+void g(vect64 *a)
+{
+  *a = __builtin_shufflevector((vect64){0}, *a, 3, 4, 5, 6);
+}
+
+/* { dg-final { scan-assembler "psllq" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr113871-5b.c b/gcc/testsuite/gcc.target/i386/pr113871-5b.c
new file mode 100644
index 00000000000..363a0f516cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr113871-5b.c
@@ -0,0 +1,19 @@ 
+/* PR target/113871 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef __bf16 vect32 __attribute__((vector_size(4)));
+
+void f (vect32 *a)
+{
+  *a = __builtin_shufflevector(*a, (vect32){0}, 1, 2);
+}
+
+/* { dg-final { scan-assembler "psrld" } } */
+
+void g(vect32 *a)
+{
+  *a = __builtin_shufflevector((vect32){0}, *a, 1, 2);
+}
+
+/* { dg-final { scan-assembler "pslld" } } */