RISC-V: add option -m(no-)autovec-segment
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Commit Message
with this recognition like aarch64:
/* Return true if an access of kind KIND for STMT_INFO represents one
vector of an LD[234] or ST[234] operation. Return the total number of
vectors (2, 3 or 4) if so, otherwise return a value outside that range. */
static int
aarch64_ld234_st234_vectors (vect_cost_for_stmt kind, stmt_vec_info stmt_info)
{
if ((kind == vector_load
|| kind == unaligned_load
|| kind == vector_store
|| kind == unaligned_store)
&& STMT_VINFO_DATA_REF (stmt_info))
{
stmt_info = DR_GROUP_FIRST_ELEMENT (stmt_info);
if (stmt_info
&& STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info) == VMAT_LOAD_STORE_LANES)
return DR_GROUP_SIZE (stmt_info);
}
return 0;
}
juzhe.zhong@rivai.ai
@@ -11521,7 +11521,8 @@ vectorizable_load (vec_info *vinfo,
- (vec_num * j + i) * nunits);
/* remain should now be > 0 and < nunits. */
unsigned num;
- if (constant_multiple_p (nunits, remain, &num))
+ if (known_gt (remain, 0)
+ && constant_multiple_p (nunits, remain, &num))
Why do you change loop vectorize code here ?
Ideally, we should add cost model for segment load/store instead of disable segment load/store autovectorization with compile option.