[v2] RISC-V: Add autovec FP unary operations.
Checks
Commit Message
Hi,
changes from V1:
- Use VF_AUTO iterator.
- Don't mention vfsqrt7.
This patch adds floating-point autovec expanders for vfneg, vfabs as well as
vfsqrt and the accompanying tests.
Similary to the binop tests, there are flavors for zvfh now.
gcc/ChangeLog:
* config/riscv/autovec.md (<optab><mode>2): Add unop expanders.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/abs-run.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/abs-template.h: Add FP.
* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/vneg-template.h: Add FP.
* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: New test.
---
gcc/config/riscv/autovec.md | 36 ++++++++++++++++++-
.../riscv/rvv/autovec/unop/abs-run.c | 6 ++--
.../riscv/rvv/autovec/unop/abs-rv32gcv.c | 3 +-
.../riscv/rvv/autovec/unop/abs-rv64gcv.c | 3 +-
.../riscv/rvv/autovec/unop/abs-template.h | 14 +++++++-
.../riscv/rvv/autovec/unop/abs-zvfh-run.c | 35 ++++++++++++++++++
.../riscv/rvv/autovec/unop/vfsqrt-run.c | 29 +++++++++++++++
.../riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c | 10 ++++++
.../riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c | 10 ++++++
.../riscv/rvv/autovec/unop/vfsqrt-template.h | 31 ++++++++++++++++
.../riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c | 32 +++++++++++++++++
.../riscv/rvv/autovec/unop/vneg-run.c | 6 ++--
.../riscv/rvv/autovec/unop/vneg-rv32gcv.c | 3 +-
.../riscv/rvv/autovec/unop/vneg-rv64gcv.c | 3 +-
.../riscv/rvv/autovec/unop/vneg-template.h | 5 ++-
.../riscv/rvv/autovec/unop/vneg-zvfh-run.c | 26 ++++++++++++++
16 files changed, 241 insertions(+), 11 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
Comments
Hi Robin,
Looks good to me except for note that this seems to depend on a new
function: emit_vlmax_fp_insn which appears to be part of your autovec FP
binary operation. So that patch would need to be merged first from what
I can see.
On 6/15/23 11:12, Robin Dapp via Gcc-patches wrote:
> Hi,
>
> changes from V1:
> - Use VF_AUTO iterator.
> - Don't mention vfsqrt7.
>
> This patch adds floating-point autovec expanders for vfneg, vfabs as well as
> vfsqrt and the accompanying tests.
>
> Similary to the binop tests, there are flavors for zvfh now.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (<optab><mode>2): Add unop expanders.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Add FP.
> * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Add FP.
> * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Add FP.
> * gcc.target/riscv/rvv/autovec/unop/abs-template.h: Add FP.
> * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Add FP.
> * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Add FP.
> * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Add FP.
> * gcc.target/riscv/rvv/autovec/unop/vneg-template.h: Add FP.
> * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: New test.
> * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: New test.
> * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: New test.
> * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: New test.
> * gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h: New test.
> * gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: New test.
> * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: New test.
> ---
> gcc/config/riscv/autovec.md | 36 ++++++++++++++++++-
> .../riscv/rvv/autovec/unop/abs-run.c | 6 ++--
> .../riscv/rvv/autovec/unop/abs-rv32gcv.c | 3 +-
> .../riscv/rvv/autovec/unop/abs-rv64gcv.c | 3 +-
> .../riscv/rvv/autovec/unop/abs-template.h | 14 +++++++-
> .../riscv/rvv/autovec/unop/abs-zvfh-run.c | 35 ++++++++++++++++++
> .../riscv/rvv/autovec/unop/vfsqrt-run.c | 29 +++++++++++++++
> .../riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c | 10 ++++++
> .../riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c | 10 ++++++
> .../riscv/rvv/autovec/unop/vfsqrt-template.h | 31 ++++++++++++++++
> .../riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c | 32 +++++++++++++++++
> .../riscv/rvv/autovec/unop/vneg-run.c | 6 ++--
> .../riscv/rvv/autovec/unop/vneg-rv32gcv.c | 3 +-
> .../riscv/rvv/autovec/unop/vneg-rv64gcv.c | 3 +-
> .../riscv/rvv/autovec/unop/vneg-template.h | 5 ++-
> .../riscv/rvv/autovec/unop/vneg-zvfh-run.c | 26 ++++++++++++++
> 16 files changed, 241 insertions(+), 11 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 94452c932a4..5b84eaaf052 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -513,7 +513,7 @@ (define_expand "<optab><mode>2"
> })
>
> ;; -------------------------------------------------------------------------------
> -;; - ABS expansion to vmslt and vneg
> +;; - [INT] ABS expansion to vmslt and vneg.
> ;; -------------------------------------------------------------------------------
>
> (define_expand "abs<mode>2"
> @@ -532,6 +532,40 @@ (define_expand "abs<mode>2"
> DONE;
> })
>
> +;; -------------------------------------------------------------------------------
> +;; ---- [FP] Unary operations
> +;; -------------------------------------------------------------------------------
> +;; Includes:
> +;; - vfneg.v/vfabs.v
> +;; -------------------------------------------------------------------------------
> +(define_expand "<optab><mode>2"
> + [(set (match_operand:VF_AUTO 0 "register_operand")
> + (any_float_unop_nofrm:VF_AUTO
> + (match_operand:VF_AUTO 1 "register_operand")))]
> + "TARGET_VECTOR"
> +{
> + insn_code icode = code_for_pred (<CODE>, <MODE>mode);
> + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
> + DONE;
> +})
> +
> +;; -------------------------------------------------------------------------------
> +;; - [FP] Square root
> +;; -------------------------------------------------------------------------------
> +;; Includes:
> +;; - vfsqrt.v
> +;; -------------------------------------------------------------------------------
> +(define_expand "<optab><mode>2"
> + [(set (match_operand:VF_AUTO 0 "register_operand")
> + (any_float_unop:VF_AUTO
> + (match_operand:VF_AUTO 1 "register_operand")))]
> + "TARGET_VECTOR"
> +{
> + insn_code icode = code_for_pred (<CODE>, <MODE>mode);
> + riscv_vector::emit_vlmax_fp_insn (icode, riscv_vector::RVV_UNOP, operands);
> + DONE;
> +})
> +
> ;; =========================================================================
> ;; == Ternary arithmetic
> ;; =========================================================================
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> index d93a7c768d2..18c7a55e23d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> @@ -1,5 +1,5 @@
> /* { dg-do run { target { riscv_vector_hw } } } */
> -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
>
> #include "abs-template.h"
>
> @@ -30,7 +30,9 @@
> RUN(int8_t) \
> RUN(int16_t) \
> RUN(int32_t) \
> - RUN(int64_t)
> + RUN(int64_t) \
> + RUN(float) \
> + RUN(double) \
>
> int main ()
> {
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
> index a8b92c9450f..dea790ccc2d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
> @@ -1,8 +1,9 @@
> /* { dg-do compile } */
> -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
>
> #include "abs-template.h"
>
> /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
> /* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
> /* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
> +/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
> index 2e7f0864ee7..b58f1aa3496 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
> @@ -1,8 +1,9 @@
> /* { dg-do compile } */
> -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
>
> #include "abs-template.h"
>
> /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
> /* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
> /* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
> +/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
> index 882de9f4efb..b86d04bfbc8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
> @@ -1,5 +1,6 @@
> #include <stdlib.h>
> #include <stdint-gcc.h>
> +#include <math.h>
>
> #define TEST_TYPE(TYPE) \
> __attribute__((noipa)) \
> @@ -17,10 +18,21 @@
> dst[i] = llabs (a[i]); \
> }
>
> +#define TEST_TYPE3(TYPE) \
> + __attribute__((noipa)) \
> + void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \
> + { \
> + for (int i = 0; i < n; i++) \
> + dst[i] = fabs (a[i]); \
> + }
> +
> #define TEST_ALL() \
> TEST_TYPE(int8_t) \
> TEST_TYPE(int16_t) \
> TEST_TYPE(int32_t) \
> - TEST_TYPE2(int64_t)
> + TEST_TYPE2(int64_t) \
> + TEST_TYPE3(_Float16) \
> + TEST_TYPE3(float) \
> + TEST_TYPE3(double) \
>
> TEST_ALL()
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
> new file mode 100644
> index 00000000000..9b1c26381d0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
> @@ -0,0 +1,35 @@
> +/* { dg-do run { target { riscv_zvfh_hw } } } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
> +
> +#include "abs-template.h"
> +
> +#include <assert.h>
> +
> +#define SZ 128
> +
> +#define RUN(TYPE) \
> + TYPE a##TYPE[SZ]; \
> + for (int i = 0; i < SZ; i++) \
> + { \
> + if (i & 1) \
> + a##TYPE[i] = i - 64; \
> + else \
> + a##TYPE[i] = i; \
> + } \
> + vabs_##TYPE (a##TYPE, a##TYPE, SZ); \
> + for (int i = 0; i < SZ; i++) \
> + { \
> + if (i & 1) \
> + assert (a##TYPE[i] == abs (i - 64)); \
> + else \
> + assert (a##TYPE[i] == i); \
> + }
> +
> +
> +#define RUN_ALL() \
> + RUN(_Float16) \
> +
> +int main ()
> +{
> + RUN_ALL()
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
> new file mode 100644
> index 00000000000..8038a87bdc9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
> @@ -0,0 +1,29 @@
> +/* { dg-do run { target { riscv_vector_hw } } } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
> +
> +#include "vfsqrt-template.h"
> +
> +#include <assert.h>
> +
> +#define SZ 255
> +
> +#define EPS 1e-5
> +
> +#define RUN(TYPE) \
> + TYPE a##TYPE[SZ]; \
> + for (int i = 0; i < SZ; i++) \
> + { \
> + a##TYPE[i] = (TYPE)i; \
> + } \
> + vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \
> + for (int i = 0; i < SZ; i++) \
> + assert (__builtin_fabs (a##TYPE[i] - __builtin_sqrtf((TYPE)i)) < EPS);
> +
> +#define RUN_ALL() \
> + RUN(float) \
> + RUN(double) \
> +
> +int main ()
> +{
> + RUN_ALL()
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
> new file mode 100644
> index 00000000000..96c6f959925
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
> +
> +#include "vfsqrt-template.h"
> +
> +/* We cannot link this without the _zfh extension so define
> + it here instead of in the template directly. */
> +TEST_TYPE3(_Float16)
> +
> +/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
> new file mode 100644
> index 00000000000..ea724e9548f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
> +
> +#include "vfsqrt-template.h"
> +
> +/* We cannot link this without the _zfh extension so define
> + it here instead of in the template directly. */
> +TEST_TYPE3(_Float16)
> +
> +/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h
> new file mode 100644
> index 00000000000..314ea646bec
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h
> @@ -0,0 +1,31 @@
> +#include <stdint-gcc.h>
> +
> +#define TEST_TYPE(TYPE) \
> + __attribute__((noipa)) \
> + void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \
> + { \
> + for (int i = 0; i < n; i++) \
> + dst[i] = __builtin_sqrtf (a[i]); \
> + }
> +
> +#define TEST_TYPE2(TYPE) \
> + __attribute__((noipa)) \
> + void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \
> + { \
> + for (int i = 0; i < n; i++) \
> + dst[i] = __builtin_sqrt (a[i]); \
> + }
> +
> +#define TEST_TYPE3(TYPE) \
> + __attribute__((noipa)) \
> + void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \
> + { \
> + for (int i = 0; i < n; i++) \
> + dst[i] = __builtin_sqrtf16 (a[i]); \
> + }
> +
> +#define TEST_ALL() \
> + TEST_TYPE(float) \
> + TEST_TYPE2(double) \
> +
> +TEST_ALL()
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
> new file mode 100644
> index 00000000000..655bc1c42dd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
> @@ -0,0 +1,32 @@
> +/* { dg-do run { target { riscv_zvfh_hw } } } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
> +
> +#include "vfsqrt-template.h"
> +
> +/* We cannot link this without the _zfh extension so define
> + it here instead of in the template directly. */
> +TEST_TYPE3(_Float16)
> +
> +#include <assert.h>
> +
> +#define SZ 255
> +
> +#define EPS 1e-5
> +
> +#define RUN(TYPE) \
> + TYPE a##TYPE[SZ]; \
> + for (int i = 0; i < SZ; i++) \
> + { \
> + a##TYPE[i] = (TYPE)i; \
> + } \
> + vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \
> + for (int i = 0; i < SZ; i++) \
> + assert (__builtin_fabs (a##TYPE[i] - __builtin_sqrtf((TYPE)i)) < EPS);
> +
> +#define RUN_ALL() \
> + RUN(_Float16) \
> +
> +int main ()
> +{
> + RUN_ALL()
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
> index 98c7f30ec56..4805538f252 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
> @@ -1,5 +1,5 @@
> /* { dg-do run { target { riscv_vector_hw } } } */
> -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
>
> #include "vneg-template.h"
>
> @@ -21,7 +21,9 @@
> RUN(int8_t) \
> RUN(int16_t) \
> RUN(int32_t) \
> - RUN(int64_t)
> + RUN(int64_t) \
> + RUN(float) \
> + RUN(double) \
>
> int main ()
> {
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
> index 69d9ebb0953..4a9ceb5faf2 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
> @@ -1,6 +1,7 @@
> /* { dg-do compile } */
> -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
>
> #include "vneg-template.h"
>
> /* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
> +/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
> index d2c2e17c13e..2c5e2bd2a0b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
> @@ -1,6 +1,7 @@
> /* { dg-do compile } */
> -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
>
> #include "vneg-template.h"
>
> /* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
> +/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
> index 93e690f3cec..892d9d72c38 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
> @@ -13,6 +13,9 @@
> TEST_TYPE(int8_t) \
> TEST_TYPE(int16_t) \
> TEST_TYPE(int32_t) \
> - TEST_TYPE(int64_t)
> + TEST_TYPE(int64_t) \
> + TEST_TYPE(_Float16) \
> + TEST_TYPE(float) \
> + TEST_TYPE(double) \
>
> TEST_ALL()
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
> new file mode 100644
> index 00000000000..e9de7a003c6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
> @@ -0,0 +1,26 @@
> +/* { dg-do run { target { riscv_zvfh_hw } } } */
> +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
> +
> +#include "vneg-template.h"
> +
> +#include <assert.h>
> +
> +#define SZ 255
> +
> +#define RUN(TYPE) \
> + TYPE a##TYPE[SZ]; \
> + for (int i = 0; i < SZ; i++) \
> + { \
> + a##TYPE[i] = i - 127; \
> + } \
> + vneg_##TYPE (a##TYPE, a##TYPE, SZ); \
> + for (int i = 0; i < SZ; i++) \
> + assert (a##TYPE[i] == -(i - 127));
> +
> +#define RUN_ALL() \
> + RUN(_Float16) \
> +
> +int main ()
> +{
> + RUN_ALL()
> +}
Add unary testcase of fp16 into zvfhmin-1.c (make sure they don't ICE and no vectorize when -march=rv64gc_zvfhmin).
Make sure we won't do wrong in case of ZVFHMIN.
/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV auto-vectorization when -march="*zvfhmin*". */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 0 "vect" } } */
Otherwise, LGTM.
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2023-06-15 23:12
To: gcc-patches; palmer; Kito Cheng; juzhe.zhong@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH v2] RISC-V: Add autovec FP unary operations.
Hi,
changes from V1:
- Use VF_AUTO iterator.
- Don't mention vfsqrt7.
This patch adds floating-point autovec expanders for vfneg, vfabs as well as
vfsqrt and the accompanying tests.
Similary to the binop tests, there are flavors for zvfh now.
gcc/ChangeLog:
* config/riscv/autovec.md (<optab><mode>2): Add unop expanders.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/abs-run.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/abs-template.h: Add FP.
* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Add FP.
* gcc.target/riscv/rvv/autovec/unop/vneg-template.h: Add FP.
* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h: New test.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: New test.
---
gcc/config/riscv/autovec.md | 36 ++++++++++++++++++-
.../riscv/rvv/autovec/unop/abs-run.c | 6 ++--
.../riscv/rvv/autovec/unop/abs-rv32gcv.c | 3 +-
.../riscv/rvv/autovec/unop/abs-rv64gcv.c | 3 +-
.../riscv/rvv/autovec/unop/abs-template.h | 14 +++++++-
.../riscv/rvv/autovec/unop/abs-zvfh-run.c | 35 ++++++++++++++++++
.../riscv/rvv/autovec/unop/vfsqrt-run.c | 29 +++++++++++++++
.../riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c | 10 ++++++
.../riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c | 10 ++++++
.../riscv/rvv/autovec/unop/vfsqrt-template.h | 31 ++++++++++++++++
.../riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c | 32 +++++++++++++++++
.../riscv/rvv/autovec/unop/vneg-run.c | 6 ++--
.../riscv/rvv/autovec/unop/vneg-rv32gcv.c | 3 +-
.../riscv/rvv/autovec/unop/vneg-rv64gcv.c | 3 +-
.../riscv/rvv/autovec/unop/vneg-template.h | 5 ++-
.../riscv/rvv/autovec/unop/vneg-zvfh-run.c | 26 ++++++++++++++
16 files changed, 241 insertions(+), 11 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 94452c932a4..5b84eaaf052 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -513,7 +513,7 @@ (define_expand "<optab><mode>2"
})
;; -------------------------------------------------------------------------------
-;; - ABS expansion to vmslt and vneg
+;; - [INT] ABS expansion to vmslt and vneg.
;; -------------------------------------------------------------------------------
(define_expand "abs<mode>2"
@@ -532,6 +532,40 @@ (define_expand "abs<mode>2"
DONE;
})
+;; -------------------------------------------------------------------------------
+;; ---- [FP] Unary operations
+;; -------------------------------------------------------------------------------
+;; Includes:
+;; - vfneg.v/vfabs.v
+;; -------------------------------------------------------------------------------
+(define_expand "<optab><mode>2"
+ [(set (match_operand:VF_AUTO 0 "register_operand")
+ (any_float_unop_nofrm:VF_AUTO
+ (match_operand:VF_AUTO 1 "register_operand")))]
+ "TARGET_VECTOR"
+{
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
+ DONE;
+})
+
+;; -------------------------------------------------------------------------------
+;; - [FP] Square root
+;; -------------------------------------------------------------------------------
+;; Includes:
+;; - vfsqrt.v
+;; -------------------------------------------------------------------------------
+(define_expand "<optab><mode>2"
+ [(set (match_operand:VF_AUTO 0 "register_operand")
+ (any_float_unop:VF_AUTO
+ (match_operand:VF_AUTO 1 "register_operand")))]
+ "TARGET_VECTOR"
+{
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::emit_vlmax_fp_insn (icode, riscv_vector::RVV_UNOP, operands);
+ DONE;
+})
+
;; =========================================================================
;; == Ternary arithmetic
;; =========================================================================
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
index d93a7c768d2..18c7a55e23d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector_hw } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "abs-template.h"
@@ -30,7 +30,9 @@
RUN(int8_t) \
RUN(int16_t) \
RUN(int32_t) \
- RUN(int64_t)
+ RUN(int64_t) \
+ RUN(float) \
+ RUN(double) \
int main ()
{
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
index a8b92c9450f..dea790ccc2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
@@ -1,8 +1,9 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "abs-template.h"
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
index 2e7f0864ee7..b58f1aa3496 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
@@ -1,8 +1,9 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "abs-template.h"
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
index 882de9f4efb..b86d04bfbc8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
@@ -1,5 +1,6 @@
#include <stdlib.h>
#include <stdint-gcc.h>
+#include <math.h>
#define TEST_TYPE(TYPE) \
__attribute__((noipa)) \
@@ -17,10 +18,21 @@
dst[i] = llabs (a[i]); \
}
+#define TEST_TYPE3(TYPE) \
+ __attribute__((noipa)) \
+ void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = fabs (a[i]); \
+ }
+
#define TEST_ALL() \
TEST_TYPE(int8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(int32_t) \
- TEST_TYPE2(int64_t)
+ TEST_TYPE2(int64_t) \
+ TEST_TYPE3(_Float16) \
+ TEST_TYPE3(float) \
+ TEST_TYPE3(double) \
TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
new file mode 100644
index 00000000000..9b1c26381d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "abs-template.h"
+
+#include <assert.h>
+
+#define SZ 128
+
+#define RUN(TYPE) \
+ TYPE a##TYPE[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ if (i & 1) \
+ a##TYPE[i] = i - 64; \
+ else \
+ a##TYPE[i] = i; \
+ } \
+ vabs_##TYPE (a##TYPE, a##TYPE, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ if (i & 1) \
+ assert (a##TYPE[i] == abs (i - 64)); \
+ else \
+ assert (a##TYPE[i] == i); \
+ }
+
+
+#define RUN_ALL() \
+ RUN(_Float16) \
+
+int main ()
+{
+ RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
new file mode 100644
index 00000000000..8038a87bdc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
@@ -0,0 +1,29 @@
+/* { dg-do run { target { riscv_vector_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+#include <assert.h>
+
+#define SZ 255
+
+#define EPS 1e-5
+
+#define RUN(TYPE) \
+ TYPE a##TYPE[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE[i] = (TYPE)i; \
+ } \
+ vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (__builtin_fabs (a##TYPE[i] - __builtin_sqrtf((TYPE)i)) < EPS);
+
+#define RUN_ALL() \
+ RUN(float) \
+ RUN(double) \
+
+int main ()
+{
+ RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
new file mode 100644
index 00000000000..96c6f959925
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+/* We cannot link this without the _zfh extension so define
+ it here instead of in the template directly. */
+TEST_TYPE3(_Float16)
+
+/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
new file mode 100644
index 00000000000..ea724e9548f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+/* We cannot link this without the _zfh extension so define
+ it here instead of in the template directly. */
+TEST_TYPE3(_Float16)
+
+/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h
new file mode 100644
index 00000000000..314ea646bec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h
@@ -0,0 +1,31 @@
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE) \
+ __attribute__((noipa)) \
+ void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = __builtin_sqrtf (a[i]); \
+ }
+
+#define TEST_TYPE2(TYPE) \
+ __attribute__((noipa)) \
+ void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = __builtin_sqrt (a[i]); \
+ }
+
+#define TEST_TYPE3(TYPE) \
+ __attribute__((noipa)) \
+ void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = __builtin_sqrtf16 (a[i]); \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE(float) \
+ TEST_TYPE2(double) \
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
new file mode 100644
index 00000000000..655bc1c42dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+/* We cannot link this without the _zfh extension so define
+ it here instead of in the template directly. */
+TEST_TYPE3(_Float16)
+
+#include <assert.h>
+
+#define SZ 255
+
+#define EPS 1e-5
+
+#define RUN(TYPE) \
+ TYPE a##TYPE[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE[i] = (TYPE)i; \
+ } \
+ vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (__builtin_fabs (a##TYPE[i] - __builtin_sqrtf((TYPE)i)) < EPS);
+
+#define RUN_ALL() \
+ RUN(_Float16) \
+
+int main ()
+{
+ RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
index 98c7f30ec56..4805538f252 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector_hw } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vneg-template.h"
@@ -21,7 +21,9 @@
RUN(int8_t) \
RUN(int16_t) \
RUN(int32_t) \
- RUN(int64_t)
+ RUN(int64_t) \
+ RUN(float) \
+ RUN(double) \
int main ()
{
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
index 69d9ebb0953..4a9ceb5faf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vneg-template.h"
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
index d2c2e17c13e..2c5e2bd2a0b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vneg-template.h"
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
index 93e690f3cec..892d9d72c38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
@@ -13,6 +13,9 @@
TEST_TYPE(int8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(int32_t) \
- TEST_TYPE(int64_t)
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(_Float16) \
+ TEST_TYPE(float) \
+ TEST_TYPE(double) \
TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
new file mode 100644
index 00000000000..e9de7a003c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vneg-template.h"
+
+#include <assert.h>
+
+#define SZ 255
+
+#define RUN(TYPE) \
+ TYPE a##TYPE[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE[i] = i - 127; \
+ } \
+ vneg_##TYPE (a##TYPE, a##TYPE, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (a##TYPE[i] == -(i - 127));
+
+#define RUN_ALL() \
+ RUN(_Float16) \
+
+int main ()
+{
+ RUN_ALL()
+}
--
2.40.1
On 6/16/23 07:44, juzhe.zhong wrote:
> lgtm
Which is good enough for me. Ok for the trunk.
jeff
@@ -513,7 +513,7 @@ (define_expand "<optab><mode>2"
})
;; -------------------------------------------------------------------------------
-;; - ABS expansion to vmslt and vneg
+;; - [INT] ABS expansion to vmslt and vneg.
;; -------------------------------------------------------------------------------
(define_expand "abs<mode>2"
@@ -532,6 +532,40 @@ (define_expand "abs<mode>2"
DONE;
})
+;; -------------------------------------------------------------------------------
+;; ---- [FP] Unary operations
+;; -------------------------------------------------------------------------------
+;; Includes:
+;; - vfneg.v/vfabs.v
+;; -------------------------------------------------------------------------------
+(define_expand "<optab><mode>2"
+ [(set (match_operand:VF_AUTO 0 "register_operand")
+ (any_float_unop_nofrm:VF_AUTO
+ (match_operand:VF_AUTO 1 "register_operand")))]
+ "TARGET_VECTOR"
+{
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
+ DONE;
+})
+
+;; -------------------------------------------------------------------------------
+;; - [FP] Square root
+;; -------------------------------------------------------------------------------
+;; Includes:
+;; - vfsqrt.v
+;; -------------------------------------------------------------------------------
+(define_expand "<optab><mode>2"
+ [(set (match_operand:VF_AUTO 0 "register_operand")
+ (any_float_unop:VF_AUTO
+ (match_operand:VF_AUTO 1 "register_operand")))]
+ "TARGET_VECTOR"
+{
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::emit_vlmax_fp_insn (icode, riscv_vector::RVV_UNOP, operands);
+ DONE;
+})
+
;; =========================================================================
;; == Ternary arithmetic
;; =========================================================================
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector_hw } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "abs-template.h"
@@ -30,7 +30,9 @@
RUN(int8_t) \
RUN(int16_t) \
RUN(int32_t) \
- RUN(int64_t)
+ RUN(int64_t) \
+ RUN(float) \
+ RUN(double) \
int main ()
{
@@ -1,8 +1,9 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "abs-template.h"
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
@@ -1,8 +1,9 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "abs-template.h"
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
@@ -1,5 +1,6 @@
#include <stdlib.h>
#include <stdint-gcc.h>
+#include <math.h>
#define TEST_TYPE(TYPE) \
__attribute__((noipa)) \
@@ -17,10 +18,21 @@
dst[i] = llabs (a[i]); \
}
+#define TEST_TYPE3(TYPE) \
+ __attribute__((noipa)) \
+ void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = fabs (a[i]); \
+ }
+
#define TEST_ALL() \
TEST_TYPE(int8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(int32_t) \
- TEST_TYPE2(int64_t)
+ TEST_TYPE2(int64_t) \
+ TEST_TYPE3(_Float16) \
+ TEST_TYPE3(float) \
+ TEST_TYPE3(double) \
TEST_ALL()
new file mode 100644
@@ -0,0 +1,35 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "abs-template.h"
+
+#include <assert.h>
+
+#define SZ 128
+
+#define RUN(TYPE) \
+ TYPE a##TYPE[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ if (i & 1) \
+ a##TYPE[i] = i - 64; \
+ else \
+ a##TYPE[i] = i; \
+ } \
+ vabs_##TYPE (a##TYPE, a##TYPE, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ if (i & 1) \
+ assert (a##TYPE[i] == abs (i - 64)); \
+ else \
+ assert (a##TYPE[i] == i); \
+ }
+
+
+#define RUN_ALL() \
+ RUN(_Float16) \
+
+int main ()
+{
+ RUN_ALL()
+}
new file mode 100644
@@ -0,0 +1,29 @@
+/* { dg-do run { target { riscv_vector_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+#include <assert.h>
+
+#define SZ 255
+
+#define EPS 1e-5
+
+#define RUN(TYPE) \
+ TYPE a##TYPE[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE[i] = (TYPE)i; \
+ } \
+ vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (__builtin_fabs (a##TYPE[i] - __builtin_sqrtf((TYPE)i)) < EPS);
+
+#define RUN_ALL() \
+ RUN(float) \
+ RUN(double) \
+
+int main ()
+{
+ RUN_ALL()
+}
new file mode 100644
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+/* We cannot link this without the _zfh extension so define
+ it here instead of in the template directly. */
+TEST_TYPE3(_Float16)
+
+/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */
new file mode 100644
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+/* We cannot link this without the _zfh extension so define
+ it here instead of in the template directly. */
+TEST_TYPE3(_Float16)
+
+/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */
new file mode 100644
@@ -0,0 +1,31 @@
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE) \
+ __attribute__((noipa)) \
+ void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = __builtin_sqrtf (a[i]); \
+ }
+
+#define TEST_TYPE2(TYPE) \
+ __attribute__((noipa)) \
+ void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = __builtin_sqrt (a[i]); \
+ }
+
+#define TEST_TYPE3(TYPE) \
+ __attribute__((noipa)) \
+ void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = __builtin_sqrtf16 (a[i]); \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE(float) \
+ TEST_TYPE2(double) \
+
+TEST_ALL()
new file mode 100644
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+/* We cannot link this without the _zfh extension so define
+ it here instead of in the template directly. */
+TEST_TYPE3(_Float16)
+
+#include <assert.h>
+
+#define SZ 255
+
+#define EPS 1e-5
+
+#define RUN(TYPE) \
+ TYPE a##TYPE[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE[i] = (TYPE)i; \
+ } \
+ vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (__builtin_fabs (a##TYPE[i] - __builtin_sqrtf((TYPE)i)) < EPS);
+
+#define RUN_ALL() \
+ RUN(_Float16) \
+
+int main ()
+{
+ RUN_ALL()
+}
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector_hw } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vneg-template.h"
@@ -21,7 +21,9 @@
RUN(int8_t) \
RUN(int16_t) \
RUN(int32_t) \
- RUN(int64_t)
+ RUN(int64_t) \
+ RUN(float) \
+ RUN(double) \
int main ()
{
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vneg-template.h"
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vneg-template.h"
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
@@ -13,6 +13,9 @@
TEST_TYPE(int8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(int32_t) \
- TEST_TYPE(int64_t)
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(_Float16) \
+ TEST_TYPE(float) \
+ TEST_TYPE(double) \
TEST_ALL()
new file mode 100644
@@ -0,0 +1,26 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vneg-template.h"
+
+#include <assert.h>
+
+#define SZ 255
+
+#define RUN(TYPE) \
+ TYPE a##TYPE[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE[i] = i - 127; \
+ } \
+ vneg_##TYPE (a##TYPE, a##TYPE, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (a##TYPE[i] == -(i - 127));
+
+#define RUN_ALL() \
+ RUN(_Float16) \
+
+int main ()
+{
+ RUN_ALL()
+}