diff mbox series

[v1] rs6000: Update powerpc test fold-vec-extract-int.p8.c

Message ID 4b2a20b9-9f52-05b5-371c-e0734e0df6b7@linux.ibm.com
State Committed
Commit 17714c08e9013b51cf8d04ac39f844d355c923f2
Headers
Series [v1] rs6000: Update powerpc test fold-vec-extract-int.p8.c |

Commit Message

Ajit Agarwal May 19, 2023, 7:40 a.m. UTC 
  Hello All:

Update powerpc tests for both le and be endian with extra removal of zero extension and sign extension.
with default ree pass for rs6000 target.

Bootstrapped and regtested on powerpc64-linux-gnu.

Thanks & Regards
Ajit

rs6000: Update powerpc test fold-vec-extract-int.p8.c

Update powerpc tests with extra zero_extend removal with default ree pass.

2023-05-19  Ajit Kumar Agarwal  <aagarwa1@linux.ibm.com>

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/fold-vec-extract-int.p8.c: Update test.
---
 gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Kewen.Lin June 13, 2023, 8:28 a.m. UTC | #1 
Hi,

on 2023/5/19 15:40, Ajit Agarwal via Gcc-patches wrote:
> Hello All:
> 
> Update powerpc tests for both le and be endian with extra removal of zero extension and sign extension.
> with default ree pass for rs6000 target.

Nice! 

> 
> Bootstrapped and regtested on powerpc64-linux-gnu.
> 
> Thanks & Regards
> Ajit
> 
> rs6000: Update powerpc test fold-vec-extract-int.p8.c

May be better to start with "testsuite:" or "testsuite, rs6000:".

> 
> Update powerpc tests with extra zero_extend removal with default ree pass.
> 
> 2023-05-19  Ajit Kumar Agarwal  <aagarwa1@linux.ibm.com>

Since there is an upstream bug tracking this, could you add one PR
marker like:

	PR testsuite/109880

OK for trunk with the PR marker added, thanks!

BR,
Kewen

> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/powerpc/fold-vec-extract-int.p8.c: Update test.
> ---
>  gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
> index 75eaf25943b..f5f953320d8 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
> @@ -13,8 +13,8 @@
>  
>  /* { dg-final { scan-assembler-times {\mvspltw\M} 3 { target lp64 } } } */
>  /* { dg-final { scan-assembler-times {\mmfvsrwz\M} 3 { target lp64 } } } */
> -/* { dg-final { scan-assembler-times {\mrldicl\M} 7 { target { le } } } } */
> -/* { dg-final { scan-assembler-times {\mrldicl\M} 4 { target { lp64 && be } } } } */
> +/* { dg-final { scan-assembler-times {\mrldicl\M} 5 { target { le } } } } */
> +/* { dg-final { scan-assembler-times {\mrldicl\M} 2 { target { lp64 && be } } } } */
>  /* { dg-final { scan-assembler-times {\msubfic\M} 3 { target { le } } } } */
>  /* { dg-final { scan-assembler-times {\msldi\M} 3  { target lp64 } } } */
>  /* { dg-final { scan-assembler-times {\mmtvsrd\M} 3 { target lp64 } } } */
Ajit Agarwal June 13, 2023, 8:39 a.m. UTC | #2 
commit 17714c08e9013b51cf8d04ac39f844d355c923f2 (HEAD -> master, origin/master, origin/HEAD)
Author: “Ajit Kumar Agarwal” <aagarwa1@linux.ibm.com>
Date:   Fri May 19 02:30:44 2023 -0500

    testsuite: Update powerpc test fold-vec-extract-int.p8.c
    
    Update powerpc tests with extra zero_extend removal with default ree pass.
    
    2023-06-13  Ajit Kumar Agarwal  <aagarwa1@linux.ibm.com>
    
    gcc/testsuite/ChangeLog:
    
            PR testsuite/109880
            * gcc.target/powerpc/fold-vec-extract-int.p8.c: Update test.

On 13/06/23 1:58 pm, Kewen.Lin wrote:
> PR testsuite/109880
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
index 75eaf25943b..f5f953320d8 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
@@ -13,8 +13,8 @@ 
 
 /* { dg-final { scan-assembler-times {\mvspltw\M} 3 { target lp64 } } } */
 /* { dg-final { scan-assembler-times {\mmfvsrwz\M} 3 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 7 { target { le } } } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 4 { target { lp64 && be } } } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 5 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 { target { lp64 && be } } } } */
 /* { dg-final { scan-assembler-times {\msubfic\M} 3 { target { le } } } } */
 /* { dg-final { scan-assembler-times {\msldi\M} 3  { target lp64 } } } */
 /* { dg-final { scan-assembler-times {\mmtvsrd\M} 3 { target lp64 } } } */