[rs6000] Tweak modulo define_insns to eliminate register copy

  Don't force target of modulo into a distinct register.

The define_insns for the modulo operation currently force the target 
register
to a distinct reg in preparation for a possible future peephole combining
div/mod. But this can lead to cases of a needless copy being inserted. Fixed
with the following patch.

Bootstrapped and regression tested on powerpc64le.
Ok for master?

-Pat


2023-02-27  Pat Haugen  <pthaugen@linux.ibm.com>

gcc/
	* config/rs6000/rs6000.md (*mod<mode>3, umod<mode>3): Add
	non-earlyclobber alternative.

gcc/testsuite/
	* gcc.target/powerpc/mod-no_copy.c: New.
  

Hi!

On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
> The define_insns for the modulo operation currently force the target 
> register
> to a distinct reg in preparation for a possible future peephole combining
> div/mod. But this can lead to cases of a needless copy being inserted. Fixed
> with the following patch.

Have you verified those peepholes still match?

Do those peepholes actually improve performance?  On new CPUs?  The code
here says
;; On machines with modulo support, do a combined div/mod the old fashioned
;; method, since the multiply/subtract is faster than doing the mod instruction
;; after a divide.
but that really should not be true: we can do the div and mod in
parallel (except in SMT4 perhaps, which we never schedule for anyway),
so that should always be strictly faster.

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/mod-no_copy.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile { target { powerpc*-*-*  } } } */

All files in gcc.target/powerpc/ test for this already.  Just leave off
the target clause here?

> +/* { dg-require-effective-target powerpc_p9modulo_ok } */

Leave out this line, because ...

> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */

... the -mcpu= forces it to true always.

> +/* Verify r3 is used as source and target, no copy inserted. */

> +/* { dg-final { scan-assembler-not {\mmr\M} } } */

That is probably good enough, yeah, since the test results in only a
handful of insns.


Segher
  

On 2/27/23 11:08 AM, Segher Boessenkool wrote:
> Hi!
> 
> On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
>> The define_insns for the modulo operation currently force the target
>> register
>> to a distinct reg in preparation for a possible future peephole combining
>> div/mod. But this can lead to cases of a needless copy being inserted. Fixed
>> with the following patch.
> 
> Have you verified those peepholes still match?

Yes, I verified the peepholes still match and transform the sequence.

> 
> Do those peepholes actually improve performance?  On new CPUs?  The code
> here says
> ;; On machines with modulo support, do a combined div/mod the old fashioned
> ;; method, since the multiply/subtract is faster than doing the mod instruction
> ;; after a divide.
> but that really should not be true: we can do the div and mod in
> parallel (except in SMT4 perhaps, which we never schedule for anyway),
> so that should always be strictly faster.
> 
Since the modulo insns were introduced in Power9, we're just talking 
Power9/Power10. On paper, I would agree that separate div/mod could be 
slightly faster to get the mod result, but if you throw in another 
independent div or mod in the insn stream then doing the peephole should 
be a clear win since that 3rd insn can execute in parallel with the 
initial divide as opposed to waiting for the one of the first div/mod to 
clear the exclusive stage of the pipe.

>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/powerpc/mod-no_copy.c
>> @@ -0,0 +1,17 @@
>> +/* { dg-do compile { target { powerpc*-*-*  } } } */
> 
> All files in gcc.target/powerpc/ test for this already.  Just leave off
> the target clause here?
> 
>> +/* { dg-require-effective-target powerpc_p9modulo_ok } */
> 
> Leave out this line, because ...
> 
>> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
> 
> ... the -mcpu= forces it to true always.

Will update.

-Pat

> 
>> +/* Verify r3 is used as source and target, no copy inserted. */
> 
>> +/* { dg-final { scan-assembler-not {\mmr\M} } } */
> 
> That is probably good enough, yeah, since the test results in only a
> handful of insns.
> 
> 
> Segher
  

Hi!

On Mon, Feb 27, 2023 at 02:12:23PM -0600, Pat Haugen wrote:
> On 2/27/23 11:08 AM, Segher Boessenkool wrote:
> >On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
> >>The define_insns for the modulo operation currently force the target
> >>register
> >>to a distinct reg in preparation for a possible future peephole combining
> >>div/mod. But this can lead to cases of a needless copy being inserted. 
> >>Fixed
> >>with the following patch.
> >
> >Have you verified those peepholes still match?
> 
> Yes, I verified the peepholes still match and transform the sequence.

Please add the testcases for that then?  Or do we have tests for it
already :-)

> >Do those peepholes actually improve performance?  On new CPUs?  The code
> >here says
> >;; On machines with modulo support, do a combined div/mod the old fashioned
> >;; method, since the multiply/subtract is faster than doing the mod 
> >instruction
> >;; after a divide.
> >but that really should not be true: we can do the div and mod in
> >parallel (except in SMT4 perhaps, which we never schedule for anyway),
> >so that should always be strictly faster.
> >
> Since the modulo insns were introduced in Power9, we're just talking 
> Power9/Power10. On paper, I would agree that separate div/mod could be 
> slightly faster to get the mod result,

"Slightly".  It takes 12 cycles for the two in parallel (64-bit, p9),
but 17 cycles for the "cheaper" sequence (divd+mulld+subf, 12+5+2).  It
is all worse if the units are busy of course, or if there are other
problems.

> but if you throw in another 
> independent div or mod in the insn stream then doing the peephole should 
> be a clear win since that 3rd insn can execute in parallel with the 
> initial divide as opposed to waiting for the one of the first div/mod to 
> clear the exclusive stage of the pipe.

That is the SMT4 case, the one we do not optimise for.  SMT2 and ST can
do four in parallel.  This means you can start a div or mod every 2nd
cycle on average, so it is very unlikely you will ever be limited by
this on real code.


Segher
  

On 2/27/23 2:53 PM, Segher Boessenkool wrote:
> Hi!
> 
> On Mon, Feb 27, 2023 at 02:12:23PM -0600, Pat Haugen wrote:
>> On 2/27/23 11:08 AM, Segher Boessenkool wrote:
>>> On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
>>>> The define_insns for the modulo operation currently force the target
>>>> register
>>>> to a distinct reg in preparation for a possible future peephole combining
>>>> div/mod. But this can lead to cases of a needless copy being inserted.
>>>> Fixed
>>>> with the following patch.
>>>
>>> Have you verified those peepholes still match?
>>
>> Yes, I verified the peepholes still match and transform the sequence.
> 
> Please add the testcases for that then?  Or do we have tests for it
> already :-)

I don't see one, but can add one.

>>> Do those peepholes actually improve performance?  On new CPUs?  The code
>>> here says
>>> ;; On machines with modulo support, do a combined div/mod the old fashioned
>>> ;; method, since the multiply/subtract is faster than doing the mod
>>> instruction
>>> ;; after a divide.
>>> but that really should not be true: we can do the div and mod in
>>> parallel (except in SMT4 perhaps, which we never schedule for anyway),
>>> so that should always be strictly faster.
>>>
>> Since the modulo insns were introduced in Power9, we're just talking
>> Power9/Power10. On paper, I would agree that separate div/mod could be
>> slightly faster to get the mod result,
> 
> "Slightly".  It takes 12 cycles for the two in parallel (64-bit, p9),
> but 17 cycles for the "cheaper" sequence (divd+mulld+subf, 12+5+2).  It
> is all worse if the units are busy of course, or if there are other
> problems.
> 
>> but if you throw in another
>> independent div or mod in the insn stream then doing the peephole should
>> be a clear win since that 3rd insn can execute in parallel with the
>> initial divide as opposed to waiting for the one of the first div/mod to
>> clear the exclusive stage of the pipe.
> 
> That is the SMT4 case, the one we do not optimise for.  SMT2 and ST can
> do four in parallel.  This means you can start a div or mod every 2nd
> cycle on average, so it is very unlikely you will ever be limited by
> this on real code.

Power9/Power10 only have 2 fixed-point divide units, and are able to 
issue 2 divides every 9/11 cycles (they aren't fully pipelined), with 
latencies of 12-24/12-25. Not saying that changes the "best case" 
scenario, just pointing out a lot of variables in play.

-Pat
  

On Mon, Feb 27, 2023 at 04:03:56PM -0600, Pat Haugen wrote:
> On 2/27/23 2:53 PM, Segher Boessenkool wrote:
> >"Slightly".  It takes 12 cycles for the two in parallel (64-bit, p9),
> >but 17 cycles for the "cheaper" sequence (divd+mulld+subf, 12+5+2).  It
> >is all worse if the units are busy of course, or if there are other
> >problems.
> >
> >>but if you throw in another
> >>independent div or mod in the insn stream then doing the peephole should
> >>be a clear win since that 3rd insn can execute in parallel with the
> >>initial divide as opposed to waiting for the one of the first div/mod to
> >>clear the exclusive stage of the pipe.
> >
> >That is the SMT4 case, the one we do not optimise for.  SMT2 and ST can
> >do four in parallel.  This means you can start a div or mod every 2nd
> >cycle on average, so it is very unlikely you will ever be limited by
> >this on real code.
> 
> Power9/Power10 only have 2 fixed-point divide units, and are able to 
> issue 2 divides every 9/11 cycles (they aren't fully pipelined), with 
> latencies of 12-24/12-25. Not saying that changes the "best case" 
> scenario, just pointing out a lot of variables in play.

The p9 UM says in no uncertain terms there are four integer dividers
(four fixed-point execution pipelines, all four capable of divides).
Is that wrong then?

Let's do actual tests on actual hardware :-)


Segher