@@ -248,8 +248,8 @@ (define_insn "prumov<mode>"
; Forcing DI reg alignment (akin to microblaze's HARD_REGNO_MODE_OK)
; does not seem efficient, and will violate TI ABI.
(define_insn "mov<mode>"
- [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r,r")
- (match_operand:MOV64 1 "general_operand" "r,m,Um,r,T,J,nF"))]
+ [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r,r,r")
+ (match_operand:MOV64 1 "general_operand" "r,m,Z,Um,r,T,J,nF"))]
""
{
switch (which_alternative)
@@ -259,8 +259,10 @@ (define_insn "mov<mode>"
case 1:
return "lb%B1o\\t%b0, %1, %S1";
case 2:
- return "fill\\t%F0, 8";
+ return "zero\\t%F0, 8";
case 3:
+ return "fill\\t%F0, 8";
+ case 4:
/* careful with overlapping source and destination regs. */
gcc_assert (GP_REG_P (REGNO (operands[0])));
gcc_assert (GP_REG_P (REGNO (operands[1])));
@@ -268,18 +270,18 @@ (define_insn "mov<mode>"
return "mov\\t%N0, %N1\;mov\\t%F0, %F1";
else
return "mov\\t%F0, %F1\;mov\\t%N0, %N1";
- case 4:
- return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
case 5:
- return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+ return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
case 6:
+ return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+ case 7:
return "ldi32\\t%F0, %w1\;ldi32\\t%N0, %W1";
default:
gcc_unreachable ();
}
}
- [(set_attr "type" "st,ld,alu,alu,alu,alu,alu")
- (set_attr "length" "4,4,4,8,8,8,16")])
+ [(set_attr "type" "st,ld,alu,alu,alu,alu,alu,alu")
+ (set_attr "length" "4,4,4,4,8,8,8,16")])
;
; load_multiple pattern(s).
new file mode 100644
@@ -0,0 +1,19 @@
+/* Loading a register with constant 0 integer value. */
+
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int
+test_set_0_si (void)
+{
+ /* Since zero-extension is free, "zero" fill is not implemented for SI. */
+ /* { dg-final { scan-assembler "ldi\\tr14(.b0)?, 0" } } */
+ return 0;
+}
+
+long long
+test_set_0_di (void)
+{
+ /* { dg-final { scan-assembler "zero\\tr14(.b0)?, 8" } } */
+ return 0;
+}