diff mbox series

[v4,7/8] i386: Add zero maskload else operand.

Message ID 20241107175753.322338-8-rdapp.gcc@gmail.com
State Committed
Commit ebf30772415cfd3fa544fc7262b28b948591538f
Headers
Series Add maskload else operand. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 fail Patch failed to apply

Commit Message

Robin Dapp Nov. 7, 2024, 5:57 p.m. UTC 
  From: Robin Dapp <rdapp@ventanamicro.com>

gcc/ChangeLog:

	* config/i386/sse.md (maskload<mode><sseintvecmodelower>):
	Call maskload<mode>..._1.
	(maskload<mode><sseintvecmodelower>_1): Rename.
---
 gcc/config/i386/sse.md | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

Comments

Hongtao Liu Nov. 8, 2024, 12:37 a.m. UTC | #1 
On Fri, Nov 8, 2024 at 1:58 AM Robin Dapp <rdapp.gcc@gmail.com> wrote:
>
> From: Robin Dapp <rdapp@ventanamicro.com>
>
> gcc/ChangeLog:
>
>         * config/i386/sse.md (maskload<mode><sseintvecmodelower>):
>         Call maskload<mode>..._1.
>         (maskload<mode><sseintvecmodelower>_1): Rename.
Ok for x86 part.
> ---
>  gcc/config/i386/sse.md | 21 ++++++++++++++++++---
>  1 file changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 22c6c817dd7..1523e2c4d75 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -28641,7 +28641,7 @@ (define_insn "<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>"
>     (set_attr "btver2_decode" "vector")
>     (set_attr "mode" "<sseinsnmode>")])
>
> -(define_expand "maskload<mode><sseintvecmodelower>"
> +(define_expand "maskload<mode><sseintvecmodelower>_1"
>    [(set (match_operand:V48_128_256 0 "register_operand")
>         (unspec:V48_128_256
>           [(match_operand:<sseintvecmode> 2 "register_operand")
> @@ -28649,13 +28649,28 @@ (define_expand "maskload<mode><sseintvecmodelower>"
>           UNSPEC_MASKMOV))]
>    "TARGET_AVX")
>
> +(define_expand "maskload<mode><sseintvecmodelower>"
> +  [(set (match_operand:V48_128_256 0 "register_operand")
> +       (unspec:V48_128_256
> +         [(match_operand:<sseintvecmode> 2 "register_operand")
> +          (match_operand:V48_128_256 1 "memory_operand")
> +          (match_operand:V48_128_256 3 "const0_operand")]
> +         UNSPEC_MASKMOV))]
> +  "TARGET_AVX"
> +{
> +  emit_insn (gen_maskload<mode><sseintvecmodelower>_1 (operands[0],
> +                                                      operands[1],
> +                                                      operands[2]));
> +  DONE;
> +})
> +
>  (define_expand "maskload<mode><avx512fmaskmodelower>"
>    [(set (match_operand:V48_AVX512VL 0 "register_operand")
>         (vec_merge:V48_AVX512VL
>           (unspec:V48_AVX512VL
>             [(match_operand:V48_AVX512VL 1 "memory_operand")]
>             UNSPEC_MASKLOAD)
> -         (match_dup 0)
> +          (match_operand:V48_AVX512VL 3 "const0_operand")
>           (match_operand:<avx512fmaskmode> 2 "register_operand")))]
>    "TARGET_AVX512F")
>
> @@ -28665,7 +28680,7 @@ (define_expand "maskload<mode><avx512fmaskmodelower>"
>           (unspec:VI12HFBF_AVX512VL
>             [(match_operand:VI12HFBF_AVX512VL 1 "memory_operand")]
>             UNSPEC_MASKLOAD)
> -         (match_dup 0)
> +          (match_operand:VI12HFBF_AVX512VL 3 "const0_operand")
>           (match_operand:<avx512fmaskmode> 2 "register_operand")))]
>    "TARGET_AVX512BW")
>
> --
> 2.47.0
>
diff mbox series

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 22c6c817dd7..1523e2c4d75 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -28641,7 +28641,7 @@  (define_insn "<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>"
    (set_attr "btver2_decode" "vector") 
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_expand "maskload<mode><sseintvecmodelower>"
+(define_expand "maskload<mode><sseintvecmodelower>_1"
   [(set (match_operand:V48_128_256 0 "register_operand")
 	(unspec:V48_128_256
 	  [(match_operand:<sseintvecmode> 2 "register_operand")
@@ -28649,13 +28649,28 @@  (define_expand "maskload<mode><sseintvecmodelower>"
 	  UNSPEC_MASKMOV))]
   "TARGET_AVX")
 
+(define_expand "maskload<mode><sseintvecmodelower>"
+  [(set (match_operand:V48_128_256 0 "register_operand")
+       (unspec:V48_128_256
+         [(match_operand:<sseintvecmode> 2 "register_operand")
+          (match_operand:V48_128_256 1 "memory_operand")
+          (match_operand:V48_128_256 3 "const0_operand")]
+         UNSPEC_MASKMOV))]
+  "TARGET_AVX"
+{
+  emit_insn (gen_maskload<mode><sseintvecmodelower>_1 (operands[0],
+						       operands[1],
+						       operands[2]));
+  DONE;
+})
+
 (define_expand "maskload<mode><avx512fmaskmodelower>"
   [(set (match_operand:V48_AVX512VL 0 "register_operand")
 	(vec_merge:V48_AVX512VL
 	  (unspec:V48_AVX512VL
 	    [(match_operand:V48_AVX512VL 1 "memory_operand")]
 	    UNSPEC_MASKLOAD)
-	  (match_dup 0)
+          (match_operand:V48_AVX512VL 3 "const0_operand")
 	  (match_operand:<avx512fmaskmode> 2 "register_operand")))]
   "TARGET_AVX512F")
 
@@ -28665,7 +28680,7 @@  (define_expand "maskload<mode><avx512fmaskmodelower>"
 	  (unspec:VI12HFBF_AVX512VL
 	    [(match_operand:VI12HFBF_AVX512VL 1 "memory_operand")]
 	    UNSPEC_MASKLOAD)
-	  (match_dup 0)
+          (match_operand:VI12HFBF_AVX512VL 3 "const0_operand")
 	  (match_operand:<avx512fmaskmode> 2 "register_operand")))]
   "TARGET_AVX512BW")