@@ -95,7 +95,7 @@ using namespace riscv_vector;
It's a bit different from bitmap_union_of_preds in cfganal.cc. This function
takes into account the case where pred is ENTRY basic block. The main reason
for this difference is to make it easier to insert some special value into
- the ENTRY base block. For example, vsetvl_info with a status of UNKNOW. */
+ the ENTRY base block. For example, vsetvl_info with a status of UNKNOWN. */
static void
bitmap_union_of_preds_with_entry (sbitmap dst, sbitmap *src, basic_block b)
{
@@ -126,9 +126,9 @@ bitmap_union_of_preds_with_entry (sbitmap dst, sbitmap *src, basic_block b)
}
}
-/* Compute the reaching defintion in and out based on the gen and KILL
- informations in each Base Blocks.
- This function references the compute_avaiable implementation in lcm.cc */
+/* Compute the reaching definition in and out based on the gen and KILL
+ information's in each Base Blocks.
+ This function references the compute_available implementation in lcm.cc */
static void
compute_reaching_defintion (sbitmap *gen, sbitmap *kill, sbitmap *in,
sbitmap *out)
@@ -719,7 +719,7 @@ get_all_predecessors (basic_block bb)
require SEW and LMUL to be fixed.
Therefore, if the former RVV instruction needs DEMAND_RATIO_P and the latter
instruction needs DEMAND_SEW_LMUL_P and its SEW/LMUL is the same as that of
- the former instruction, then we can make the minimu demand of the former
+ the former instruction, then we can make the minimum demand of the former
instruction strict to DEMAND_SEW_LMUL_P, and its required SEW and LMUL are
the SEW and LMUL of the latter instruction, and the vsetvl instruction
generated according to the new demand can also be used for the latter
@@ -741,7 +741,7 @@ enum demand_flags : unsigned
/* We split the demand information into three parts. They are sew and lmul
related (sew_lmul_demand_type), tail and mask policy related
(policy_demand_type) and avl related (avl_demand_type). Then we define three
- interfaces avaiable_with, compatible_p and merge. avaiable_with is
+ interfaces available_p, compatible_p and merge. available_p is
used to determine whether the two vsetvl infos prev_info and next_info are
available or not. If prev_info is available for next_info, it means that the
RVV insn corresponding to next_info on the path from prev_info to next_info
@@ -1361,17 +1361,17 @@ public:
/* Demand system is the RVV-based VSETVL info analysis tools wrapper.
It defines compatible rules for SEW/LMUL, POLICY and AVL.
- Also, it provides 3 iterfaces avaiable_p, compatible_p and
+ Also, it provides 3 interfaces available_p, compatible_p and
merge for the VSETVL PASS analysis and optimization.
- - avaiable_p: Determine whether the next info can get the
- avaiable VSETVL status from previous info.
+ - available_p: Determine whether the next info can get the
+ available VSETVL status from previous info.
e.g. bb 2 (demand SEW = 32, LMUL = M2) -> bb 3 (demand RATIO = 16).
Since bb 2 demand info (SEW/LMUL = 32/2 = 16) satisfies the bb 3
demand, the VSETVL instruction in bb 3 can be elided.
- avaiable_p (previous, next) is true in such situation.
+ available_p (previous, next) is true in such situation.
- compatible_p: Determine whether prev_info is compatible with next_info
- so that we can have a new merged info that is avaiable to both of them.
+ so that we can have a new merged info that is available to both of them.
- merge: Merge the stricter demand information from
next_info into prev_info so that prev_info becomes available to
next_info. */
@@ -1873,7 +1873,7 @@ public:
for (insn_info *i = next_insn; i != next_insn->bb ()->head_insn ();
i = i->prev_nondebug_insn ())
{
- // no def amd use of vl
+ // no def and use of vl
if (!ignore_vl && modify_or_use_vl_p (i, info))
return false;
@@ -1885,7 +1885,7 @@ public:
for (insn_info *i = prev_insn->bb ()->end_insn (); i != prev_insn;
i = i->prev_nondebug_insn ())
{
- // no def amd use of vl
+ // no def mad use of vl
if (!ignore_vl && modify_or_use_vl_p (i, info))
return false;
@@ -2106,11 +2106,11 @@ private:
demand_system m_dem;
auto_vec<vsetvl_block_info> m_vector_block_infos;
- /* data for avl reaching defintion. */
+ /* data for avl reaching definition. */
sbitmap *m_reg_def_loc;
- /* data for vsetvl info reaching defintion. */
- vsetvl_info m_unknow_info;
+ /* data for vsetvl info reaching definition. */
+ vsetvl_info m_unknown_info;
auto_vec<vsetvl_info *> m_vsetvl_def_exprs;
sbitmap *m_vsetvl_def_in;
sbitmap *m_vsetvl_def_out;
@@ -2209,9 +2209,9 @@ private:
auto &new_prob = get_block_info (e->dest).probability;
/* Normally, the edge probability should be initialized.
However, some special testing code which is written in
- GIMPLE IR style force the edge probility uninitialized,
+ GIMPLE IR style force the edge probability uninitialized,
we conservatively set it as never so that it will not
- affect PRE (Phase 3 && Phse 4). */
+ affect PRE (Phase 3 && Phase 4). */
if (!e->probability.initialized_p ())
new_prob = profile_probability::never ();
else if (!new_prob.initialized_p ())
@@ -2307,7 +2307,7 @@ private:
continue;
else
/* We pick the highest probability among those incompatible VSETVL
- infos. When all incompatible VSTEVL infos have same probability, we
+ infos. When all incompatible VSETVL infos have same probability, we
don't pick any of them. */
return false;
}
@@ -2365,7 +2365,7 @@ public:
crtl->ssa = new function_info (cfun);
m_vector_block_infos.safe_grow_cleared (last_basic_block_for_fn (cfun));
compute_probabilities ();
- m_unknow_info.set_unknown ();
+ m_unknown_info.set_unknown ();
}
void finish ()
@@ -2414,7 +2414,7 @@ public:
bool earliest_fuse_vsetvl_info (int iter);
void pre_global_vsetvl_info ();
void emit_vsetvl ();
- void cleaup ();
+ void cleanup ();
void remove_avl_operand ();
void remove_unused_dest_operand ();
void remove_vsetvl_pre_insns ();
@@ -2450,7 +2450,7 @@ void
pre_vsetvl::compute_vsetvl_def_data ()
{
m_vsetvl_def_exprs.truncate (0);
- add_expr (m_vsetvl_def_exprs, m_unknow_info);
+ add_expr (m_vsetvl_def_exprs, m_unknown_info);
for (const bb_info *bb : crtl->ssa->bbs ())
{
vsetvl_block_info &block_info = get_block_info (bb);
@@ -2495,7 +2495,7 @@ pre_vsetvl::compute_vsetvl_def_data ()
bitmap_set_bit (m_kill[bb->index ()], i);
bitmap_set_bit (def_loc[bb->index ()],
get_expr_index (m_vsetvl_def_exprs,
- m_unknow_info));
+ m_unknown_info));
}
}
continue;
@@ -2507,10 +2507,10 @@ pre_vsetvl::compute_vsetvl_def_data ()
get_expr_index (m_vsetvl_def_exprs, footer_info));
}
- /* Set the def_out of the ENTRY basic block to m_unknow_info expr. */
+ /* Set the def_out of the ENTRY basic block to m_unknown_info expr. */
basic_block entry = ENTRY_BLOCK_PTR_FOR_FN (cfun);
bitmap_set_bit (m_vsetvl_def_out[entry->index],
- get_expr_index (m_vsetvl_def_exprs, m_unknow_info));
+ get_expr_index (m_vsetvl_def_exprs, m_unknown_info));
compute_reaching_defintion (def_loc, m_kill, m_vsetvl_def_in,
m_vsetvl_def_out);
@@ -2518,7 +2518,7 @@ pre_vsetvl::compute_vsetvl_def_data ()
if (dump_file && (dump_flags & TDF_DETAILS))
{
fprintf (dump_file,
- "\n Compute vsetvl info reaching defition data:\n\n");
+ "\n Compute vsetvl info reaching definition data:\n\n");
fprintf (dump_file, " Expression List (%d):\n",
m_vsetvl_def_exprs.length ());
for (unsigned i = 0; i < m_vsetvl_def_exprs.length (); i++)
@@ -2803,7 +2803,7 @@ pre_vsetvl::fuse_local_vsetvl_info ()
if (dump_file && (dump_flags & TDF_DETAILS))
{
fprintf (dump_file,
- " Cannot fuse uncompatible infos:\n");
+ " Cannot fuse incompatible infos:\n");
fprintf (dump_file, " prev_info: ");
prev_info.dump (dump_file, " ");
fprintf (dump_file, " curr_info: ");
@@ -3179,7 +3179,7 @@ pre_vsetvl::pre_global_vsetvl_info ()
}
}
- /* Remove vsetvl infos if all precessors are available to the block. */
+ /* Remove vsetvl infos if all predecessors are available to the block. */
for (const bb_info *bb : crtl->ssa->bbs ())
{
vsetvl_block_info &block_info = get_block_info (bb);
@@ -3370,7 +3370,7 @@ pre_vsetvl::emit_vsetvl ()
}
void
-pre_vsetvl::cleaup ()
+pre_vsetvl::cleanup ()
{
remove_avl_operand ();
remove_unused_dest_operand ();
@@ -3564,10 +3564,10 @@ pass_vsetvl::lazy_vsetvl ()
"\nPhase 4: Insert, modify and remove vsetvl insns.\n\n");
pre.emit_vsetvl ();
- /* Phase 5: Cleaup */
+ /* Phase 5: Cleanup */
if (dump_file)
- fprintf (dump_file, "\nPhase 5: Cleaup\n\n");
- pre.cleaup ();
+ fprintf (dump_file, "\nPhase 5: Cleanup\n\n");
+ pre.cleanup ();
pre.finish ();
}
@@ -203,7 +203,7 @@ struct GTY(()) machine_function {
not be considered by the prologue and epilogue. */
bool reg_is_wrapped_separately[FIRST_PSEUDO_REGISTER];
- /* The mode swithching information for the FRM rounding modes. */
+ /* The mode switching information for the FRM rounding modes. */
struct mode_switching_info mode_sw_info;
};
@@ -1464,7 +1464,7 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode,
if (!riscv_split_symbol_type (sym_type))
return false;
- /* We can't tell size or alignment when we have BLKmode, so try extracing a
+ /* We can't tell size or alignment when we have BLKmode, so try extracting a
decl from the symbol if possible. */
if (mode == BLKmode)
{
@@ -1503,7 +1503,7 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode,
/* Return true if mode is the RVV enabled mode.
For example: 'RVVMF2SI' mode is disabled,
- wheras 'RVVM1SI' mode is enabled if MIN_VLEN == 32. */
+ whereas 'RVVM1SI' mode is enabled if MIN_VLEN == 32. */
bool
riscv_v_ext_vector_mode_p (machine_mode mode)
@@ -2377,7 +2377,7 @@ riscv_force_address (rtx x, machine_mode mode)
else
{
/* It's only safe for the thunk function.
- Use ra as the temp regiater. */
+ Use ra as the temp register. */
gcc_assert (riscv_in_thunk_func);
rtx reg = RISCV_PROLOGUE_TEMP2 (Pmode);
riscv_emit_move (reg, x);
@@ -2786,7 +2786,7 @@ void
riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src)
{
poly_int64 value = rtx_to_poly_int64 (src);
- /* It use HOST_WIDE_INT intead of int since 32bit type is not enough
+ /* It use HOST_WIDE_INT instead of int since 32bit type is not enough
for e.g. (const_poly_int:DI [549755813888, 549755813888]). */
HOST_WIDE_INT offset = value.coeffs[0];
HOST_WIDE_INT factor = value.coeffs[1];
@@ -3175,7 +3175,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
/* RISC-V GCC may generate non-legitimate address due to we provide some
pattern for optimize access PIC local symbol and it's make GCC generate
- unrecognizable instruction during optmizing. */
+ unrecognizable instruction during optimizing. */
if (MEM_P (dest) && !riscv_legitimate_address_p (mode, XEXP (dest, 0),
reload_completed))
@@ -3235,7 +3235,7 @@ riscv_immediate_operand_p (int code, HOST_WIDE_INT x)
}
/* Return the cost of binary operation X, given that the instruction
- sequence for a word-sized or smaller operation takes SIGNLE_INSNS
+ sequence for a word-sized or smaller operation takes SINGLE_INSNS
instructions and that the sequence of a double-word operation takes
DOUBLE_INSNS instructions. */
@@ -6079,7 +6079,7 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc)
fputc (')', file);
}
-/* Return the memory model that encapuslates both given models. */
+/* Return the memory model that encapsulates both given models. */
enum memmodel
riscv_union_memmodels (enum memmodel model1, enum memmodel model2)
@@ -6545,7 +6545,7 @@ riscv_in_small_data_p (const_tree x)
{
/* Because default_use_anchors_for_symbol_p doesn't gather small data to use
the anchor symbol to address nearby objects. In large model, it can get
- the better result using the anchor optiomization. */
+ the better result using the anchor optimization. */
if (riscv_cmodel == CM_LARGE)
return false;
@@ -7455,7 +7455,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame, poly_int64 remaining_siz
remaining_const_size = remaining_size.to_constant ();
/* First step must be set to the top of vector registers save area if any
- vector registers need be preversed. */
+ vector registers need be preserved. */
if (frame->vmask != 0)
return (remaining_size - frame->v_sp_offset_top).to_constant ();
@@ -7649,7 +7649,7 @@ riscv_expand_prologue (void)
if (cfun->machine->naked_p)
return;
- /* prefer muti-push to save-restore libcall. */
+ /* prefer multi-push to save-restore libcall. */
if (riscv_use_multi_push (frame))
{
remaining_size -= frame->multi_push_adj_base;
@@ -7685,7 +7685,7 @@ riscv_expand_prologue (void)
/* Temporarily fib that we need not save GPRs. */
frame->mask = 0;
- /* push FPRs into the addtional reserved space by cm.push. */
+ /* push FPRs into the additional reserved space by cm.push. */
if (fmask)
{
unsigned mask_fprs_push
@@ -8066,7 +8066,7 @@ riscv_expand_epilogue (int style)
poly_int64 step1;
/* STEP1 must be set to the bottom of vector registers save area if any
- vector registers need be preversed. */
+ vector registers need be preserved. */
if (frame->vmask != 0)
{
step1 = frame->v_sp_offset_bottom;
@@ -9315,7 +9315,7 @@ riscv_convert_vector_chunks (struct gcc_options *opts)
int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
if (min_vlen > 32)
{
- /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
+ /* When targeting minimum VLEN > 32, we should use 64-bit chunk size.
Otherwise we can not include SEW = 64bits.
Runtime invariant: The single indeterminate represent the
number of 64-bit chunks in a vector beyond minimum length of 64 bits.
@@ -9335,7 +9335,7 @@ riscv_convert_vector_chunks (struct gcc_options *opts)
}
else
{
- /* When targetting minimum VLEN = 32, we should use 32-bit
+ /* When targeting minimum VLEN = 32, we should use 32-bit
chunk size. Runtime invariant: The single indeterminate represent the
number of 32-bit chunks in a vector beyond minimum length of 32 bits.
Thus the number of bytes in a vector is 4 + 4 * x1 which is
@@ -9403,7 +9403,7 @@ riscv_override_options_internal (struct gcc_options *opts)
riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access
|| TARGET_STRICT_ALIGN);
- /* Make a note if user explicity passed -mstrict-align for later
+ /* Make a note if user explicitly passed -mstrict-align for later
builtin macro generation. Can't use target_flags_explicitly since
it is set even for -mno-strict-align. */
riscv_user_wants_strict_align = TARGET_STRICT_ALIGN_OPTS_P (opts);
@@ -9880,7 +9880,7 @@ riscv_get_interrupt_type (tree decl)
times on a single function so use aarch64_previous_fndecl to avoid
setting up identical state. */
-/* Sanity cheching for above function attributes. */
+/* Sanity checking for above function attributes. */
static void
riscv_set_current_function (tree decl)
{
@@ -11050,7 +11050,7 @@ get_common_costs (const cpu_vector_cost *costs, tree vectype)
}
/* Return the CPU vector costs according to -mtune if tune info has non-NULL
- vector cost. Otherwide, return the default generic vector costs. */
+ vector cost. Otherwise, return the default generic vector costs. */
const cpu_vector_cost *
get_vector_costs ()
{