RISC-V: Add has compatible check for conflict vsetvl fusion

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index df7ed149388..76e3d2eb471 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2254,6 +2254,22 @@  private:
     return true;
   }
 
+  bool has_compatible_reaching_vsetvl_p (vsetvl_info info)
+  {
+    unsigned int index;
+    sbitmap_iterator sbi;
+    EXECUTE_IF_SET_IN_BITMAP (m_vsetvl_def_in[info.get_bb ()->index ()], 0,
+			      index, sbi)
+      {
+	const auto prev_info = *m_vsetvl_def_exprs[index];
+	if (!prev_info.valid_p ())
+	  continue;
+	if (m_dem.compatible_p (prev_info, info))
+	  return true;
+      }
+    return false;
+  }
+
   bool preds_all_same_avl_and_ratio_p (const vsetvl_info &curr_info)
   {
     gcc_assert (
@@ -3075,22 +3091,8 @@  pre_vsetvl::earliest_fuse_vsetvl_info ()
 	    {
 	      vsetvl_info new_curr_info = curr_info;
 	      new_curr_info.set_bb (crtl->ssa->bb (eg->dest));
-	      bool has_compatible_p = false;
-	      unsigned int def_expr_index;
-	      sbitmap_iterator sbi2;
-	      EXECUTE_IF_SET_IN_BITMAP (
-		m_vsetvl_def_in[new_curr_info.get_bb ()->index ()], 0,
-		def_expr_index, sbi2)
-		{
-		  vsetvl_info &prev_info = *m_vsetvl_def_exprs[def_expr_index];
-		  if (!prev_info.valid_p ())
-		    continue;
-		  if (m_dem.compatible_p (prev_info, new_curr_info))
-		    {
-		      has_compatible_p = true;
-		      break;
-		    }
-		}
+	      bool has_compatible_p
+		= has_compatible_reaching_vsetvl_p (new_curr_info);
 	      if (!has_compatible_p)
 		{
 		  if (dump_file && (dump_flags & TDF_DETAILS))
@@ -3146,7 +3148,10 @@  pre_vsetvl::earliest_fuse_vsetvl_info ()
 		       && !m_dem.compatible_p (prev_info, curr_info))
 		{
 		  /* Cancel lift up if probabilities are equal.  */
-		  if (successors_probability_equal_p (eg->src))
+		  if (successors_probability_equal_p (eg->src)
+		      || (dest_block_info.probability
+			    > src_block_info.probability
+			  && !has_compatible_reaching_vsetvl_p (curr_info)))
 		    {
 		      if (dump_file && (dump_flags & TDF_DETAILS))
 			{
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/ppgrid.mod b/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/ppgrid.mod
new file mode 100644
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GIT binary patch
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literal 0
HcmV?d00001

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/pr113429.f90 b/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/pr113429.f90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/pr113429.f90
@@ -0,0 +1,110 @@ 
+! { dg-do compile }
+! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -std=legacy" }
+
+module a
+  use shr_kind_mod,    b => shr_kind_r8
+  use ppgrid 
+                     
+   real(b) c          
+   real(b) aa       
+   real(b) ab  
+      
+   real(b) d         
+   real(b) e         
+contains
+subroutine f  
+   real(b)  g(pver)
+   real(b)  ac(pver)
+   real(b)  h(pver)
+   real(b)  ad(pver)        
+   real(b)  ae(pver)    
+   integer j(pcols)                           
+   integer l(pcols)                         
+   real(b) m(pver)              
+   real(b) n(pver)              
+   real(b) o(pver)              
+   real(b) y(pver)              
+   real(b) af(pver)              
+   real(b) ag(pver)             
+   real(b) ah(pver)           
+   real(b) ai(pver)           
+   real(b) aj(pcols)                
+   real(b) r(pcols)                    
+   integer ak(pcols)        
+   integer al(pcols)
+   real(b) am(pver)              
+   real(b) an(pver)              
+   real(b) ao(pver)              
+   real(b) ap(pver)            
+   real(b) aq(pver)              
+   real(b) ar(pver)              
+   real(b) as(pver)              
+   real(b) at(pver)            
+   real(b) au(pver)
+   real(b) av(pcols)                   
+   call aw(ax   , m      ,n      ,o      ,y      ,af      , ag     ,as      ,aq      ,ar      ,ao      , ac      ,g      ,h      ,an      ,am      , ap    ,at    ,ad      ,ai   ,ah     , au     ,ae ,av      ,aj   ,r     , ak    ,al    ,j      ,l    ,1       , lengath ,d    ,e    ,aa   ,c      , ay     ,ab    )
+   call az(lengath          )
+   
+    
+end  
+subroutine aw(ax   , q       ,t       ,p       ,z       ,s       , ba      ,as      ,aq      ,ar      ,ao      , ac      ,g      ,h      ,an      ,am      , ap    ,at    ,ad      ,bb    ,u      , bc      ,ae ,av      ,bd    ,be      , bf     ,bg     ,j      ,bh      ,il1g    , il2g    ,bi      ,e    ,bj      ,c      , ay     ,ab )
+   real(b)  q(pver)         
+   real(b)  t(pver)         
+   real(b)  p(pver)         
+   real(b)  av(pcols)             
+   real(b)  z(pver)         
+   real(b)  s(pver)         
+   real(b)  ba(pver)        
+   real(b)  as(pver)        
+   real(b)  aq(pver)        
+   real(b)  ar(pver)        
+   real(b)  ao(pver)        
+   real(b)  ac(pver)        
+   real(b)  g(pver)        
+   real(b)  h(pver)        
+   real(b)  an(pver)        
+   real(b)  am(pver)        
+   real(b)  ap(pver)      
+   real(b)  at(pver)      
+   real(b)  ad(pver)        
+   real(b)  bb(pver)      
+   real(b)  u(1)      
+   real(b)  bc(pver)        
+   real(b)  bd(pcols)           
+   real(b)  be(pcols)
+   real(b)  ae(pcols)        
+   integer bf(pcols)         
+   integer bg(pcols)         
+   integer j(pcols)          
+   integer bh(pcols)          
+   real bk(pcols,pver)
+   real bl(pcols)
+   real(b) ab
+   real(b) bj
+   real(b) bm(pcols)
+   real(b) e
+   real(b) bi
+   real(b) c
+   do i = il1g,il2g
+      bl(i) = 2
+   end do
+   do k = 1,pver
+      do i = il1g,il1g
+      if (k <= v) then
+            w = bl(i)
+            bk = w 
+         end if
+      end do
+   end do
+   bm(:il2g)  = 0.
+   bn = minval(bg(:il2g))
+   do k = bn, bo
+      do i = il1g,il2g
+         if ( k <= 1) then
+            bm = bk(i,x)
+         endif
+      end do
+   av = bp(bm)
+   end do
+end  
+end 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/shr_kind_mod.mod b/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/shr_kind_mod.mod
new file mode 100644
index 0000000000000000000000000000000000000000..b2d4df243182c9658d6fb4448d9f1949c8b71394
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
@@ -40,6 +40,8 @@  dg-init
 # Main loop.
 gfortran-dg-runtest [lsort \
    [glob -nocomplain $srcdir/$subdir/fortran/*.\[fF\]{,90,95,03,08} ] ] "" ""
+gfortran-dg-runtest [lsort \
+   [glob -nocomplain $srcdir/$subdir/fortran/spec2017_cam4/*.\[fF\]{,90,95,03,08} ] ] "" ""
 
 # All done.
 dg-finish
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
index 28ffe2c687a..dedbc94fb29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
@@ -23,7 +23,6 @@  void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, si
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]:+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
index cd94fdae4b4..26db192d836 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
@@ -17,15 +17,13 @@  void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, si
         vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 300);
         *(vuint16mf2_t*)(out + i + 300) = v;
       } else {
-        vbool1_t v = *(vbool1_t*)(in + i + 400);
-        *(vbool1_t*)(out + i + 400) = v;
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 400);
+        *(vint8mf8_t*)(out + i + 400) = v;
       }
     }
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */