diff mbox series

[gcc-wwwdocs,v2] gcc-13/14: Mention recent update for x86_64 backend

Message ID 20231221082558.449203-1-haochen.jiang@intel.com
State New
Headers
Series [gcc-wwwdocs,v2] gcc-13/14: Mention recent update for x86_64 backend |

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linaro-tcwg-bot/tcwg_gcc_build--master-arm fail Patch failed to apply
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Commit Message

Jiang, Haochen Dec. 21, 2023, 8:25 a.m. UTC 
  Hi all,

This is the v2 patch for the wwwdocs change regarding to review.

If there is no objection, I will push this change next Tuesday.

Changes is v2:

  - Remove RAO-INT from Grand Ridge
  - Remove the mask register restriction for -mno-evex512
  - Arrange the options alphabetically
  - Other minor text change

Thx,
Haochen

Messages in v1:

This patch will mention the following changes in wwwdocs for x86_64 backend:

  - AVX10.1 support
  - APX EGPR, PUSH2POP2, PPX and NDD support
  - Xeon Phi ISAs deprecated

Also I adjust the words in x86_64 part for GCC 13.

---
Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14.
Also adjust documentation in GCC 13.
---
 htdocs/gcc-13/changes.html | 38 ++++++++++++++++++++------------------
 htdocs/gcc-14/changes.html | 27 ++++++++++++++++++++++-----
 2 files changed, 42 insertions(+), 23 deletions(-)

Comments

Jiang, Haochen Dec. 27, 2023, 8:29 a.m. UTC | #1 
> -----Original Message-----
> From: Haochen Jiang <haochen.jiang@intel.com>
> Sent: Thursday, December 21, 2023 4:26 PM
> To: gcc-patches@gcc.gnu.org
> Cc: ubizjak@gmail.com; Liu, Hongtao <hongtao.liu@intel.com>;
> gerald@pfeifer.com
> Subject: [gcc-wwwdocs PATCH v2] gcc-13/14: Mention recent update for
> x86_64 backend
> 
> Hi all,
> 
> This is the v2 patch for the wwwdocs change regarding to review.
> 
> If there is no objection, I will push this change next Tuesday.

I will commit the doc change patch.

Thx,
Haochen

> 
> Changes is v2:
> 
>   - Remove RAO-INT from Grand Ridge
>   - Remove the mask register restriction for -mno-evex512
>   - Arrange the options alphabetically
>   - Other minor text change
> 
> Thx,
> Haochen
> 
> Messages in v1:
> 
> This patch will mention the following changes in wwwdocs for x86_64
> backend:
> 
>   - AVX10.1 support
>   - APX EGPR, PUSH2POP2, PPX and NDD support
>   - Xeon Phi ISAs deprecated
> 
> Also I adjust the words in x86_64 part for GCC 13.
> 
> ---
> Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14.
> Also adjust documentation in GCC 13.
> ---
>  htdocs/gcc-13/changes.html | 38 ++++++++++++++++++++------------------
>  htdocs/gcc-14/changes.html | 27 ++++++++++++++++++++++-----
>  2 files changed, 42 insertions(+), 23 deletions(-)
> 
> diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index
> d3bacc16..b4b1a39a 100644
> --- a/htdocs/gcc-13/changes.html
> +++ b/htdocs/gcc-13/changes.html
> @@ -543,24 +543,28 @@ You may also want to check out our
>    <code>__bf16</code> type to x86 psABI. Users need to adjust their
>    AVX512BF16-related source code when upgrading GCC12 to GCC13.
>    </li>
> -  <li>New ISA extension support for Intel AVX-IFMA was added.
> -      AVX-IFMA intrinsics are available via the <code>-mavxifma</code>
> +  <li>New ISA extension support for Intel AMX-COMPLEX was added.
> +      AMX-COMPLEX intrinsics are available via the
> + <code>-mamx-complex</code>
>        compiler switch.
>    </li>
> -  <li>New ISA extension support for Intel AVX-VNNI-INT8 was added.
> -      AVX-VNNI-INT8 intrinsics are available via the <code>-
> mavxvnniint8</code>
> +  <li>New ISA extension support for Intel AMX-FP16 was added.
> +      AMX-FP16 intrinsics are available via the <code>-mamx-fp16</code>
> +      compiler switch.
> +  </li>
> +  <li>New ISA extension support for Intel AVX-IFMA was added.
> +      AVX-IFMA intrinsics are available via the <code>-mavxifma</code>
>        compiler switch.
>    </li>
>    <li>New ISA extension support for Intel AVX-NE-CONVERT was added.
>        AVX-NE-CONVERT intrinsics are available via the
>        <code>-mavxneconvert</code> compiler switch.
>    </li>
> -  <li>New ISA extension support for Intel CMPccXADD was added.
> -      CMPccXADD intrinsics are available via the <code>-mcmpccxadd</code>
> +  <li>New ISA extension support for Intel AVX-VNNI-INT8 was added.
> +      AVX-VNNI-INT8 intrinsics are available via the
> + <code>-mavxvnniint8</code>
>        compiler switch.
>    </li>
> -  <li>New ISA extension support for Intel AMX-FP16 was added.
> -      AMX-FP16 intrinsics are available via the <code>-mamx-fp16</code>
> +  <li>New ISA extension support for Intel CMPccXADD was added.
> +      CMPccXADD intrinsics are available via the
> + <code>-mcmpccxadd</code>
>        compiler switch.
>    </li>
>    <li>New ISA extension support for Intel PREFETCHI was added.
> @@ -571,10 +575,6 @@ You may also want to check out our
>        RAO-INT intrinsics are available via the <code>-mraoint</code>
>        compiler switch.
>    </li>
> -  <li>New ISA extension support for Intel AMX-COMPLEX was added.
> -      AMX-COMPLEX intrinsics are available via the <code>-mamx-
> complex</code>
> -      compiler switch.
> -  </li>
>    <li>GCC now supports the Intel CPU named Raptor Lake through
>      <code>-march=raptorlake</code>.
>      Raptor Lake is based on Alder Lake.
> @@ -585,13 +585,13 @@ You may also want to check out our
>    </li>
>    <li>GCC now supports the Intel CPU named Sierra Forest through
>      <code>-march=sierraforest</code>.
> -    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT,
> CMPccXADD,
> -    ENQCMD and UINTR ISA extensions.
> +    Based on ISA extensions enabled on Alder Lake, the switch further enables
> +    the AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPccXADD,
> ENQCMD and UINTR
> +    ISA extensions.
>    </li>
>    <li>GCC now supports the Intel CPU named Grand Ridge through
>      <code>-march=grandridge</code>.
> -    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT,
> CMPccXADD,
> -    ENQCMD, UINTR and RAO-INT ISA extensions.
> +    Grand Ridge is based on Sierra Forest.
>    </li>
>    <li>GCC now supports the Intel CPU named Emerald Rapids through
>      <code>-march=emeraldrapids</code>.
> @@ -599,11 +599,13 @@ You may also want to check out our
>    </li>
>    <li>GCC now supports the Intel CPU named Granite Rapids through
>      <code>-march=graniterapids</code>.
> -    The switch enables the AMX-FP16 and PREFETCHI ISA extensions.
> +    Based on Sapphire Rapids, the switch further enables the AMX-FP16 and
> +    PREFETCHI ISA extensions.
>    </li>
>    <li>GCC now supports the Intel CPU named Granite Rapids D through
>      <code>-march=graniterapids-d</code>.
> -    The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA
> extensions.
> +    Based on Granite Rapids, the switch further enables the AMX-COMPLEX
> ISA
> +    extensions.
>    </li>
>    <li>GCC now supports AMD CPUs based on the <code>znver4</code> core
>      via <code>-march=znver4</code>.  The switch makes GCC consider diff --git
> a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index
> 24e6409a..4b83037a 100644
> --- a/htdocs/gcc-14/changes.html
> +++ b/htdocs/gcc-14/changes.html
> @@ -320,8 +320,18 @@ a work-in-progress.</p>
>  <h3 id="x86">IA-32/x86-64</h3>
>  <ul>
>    <li>New compiler option <code>-m[no-]evex512</code> was added.
> -      The compiler switch enables/disables 512 bit vector and 64 bit mask
> -      register. It will be default on if AVX512F is enabled.
> +      The compiler switch enables/disables 512-bit vector.
> +      It will be default on if AVX512F is enabled.
> +  </li>
> +  <li>Part of new feature support for Intel APX was added, including EGPR,
> +      NDD, PPX and PUSH2POP2. APX support is available via the
> +      <code>-mapxf</code> compiler switch.
> +  </li>
> +  <li>New ISA extension support for Intel AVX10.1 was added.
> +      AVX10.1 intrinsics are available via the <code>-mavx10.1</code> or
> +      <code>-mavx10.1-256</code> compiler switch with 256-bit vector size
> +      support. 512-bit vector size support for AVX10.1 intrinsics are
> +      available via the <code>-mavx10.1-512</code> compiler switch.
>    </li>
>    <li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
>        AVX-VNNI-INT16 intrinsics are available via the <code>-
> mavxvnniint16</code> @@ -346,13 +356,12 @@ a work-in-progress.</p>
>    <li>GCC now supports the Intel CPU named Clearwater Forest through
>      <code>-march=clearwaterforest</code>.
>      Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
> -    SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions.
> -    extensions.
> +    PREFETCHI, SHA512, SM3, SM4 and USER_MSR ISA extensions.
>    </li>
>    <li>GCC now supports the Intel CPU named Arrow Lake through
>      <code>-march=arrowlake</code>.
>      Based on Alder Lake, the switch further enables the AVX-IFMA,
> -    AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions.
> +    AVX-NE-CONVERT, AVX-VNNI-INT8 and CMPccXADD ISA extensions.
>    </li>
>    <li>GCC now supports the Intel CPU named Arrow Lake S through
>      <code>-march=arrowlake-s</code>.
> @@ -368,6 +377,14 @@ a work-in-progress.</p>
>      Based on Arrow Lake S, the switch further enables the PREFETCHI ISA
>      extensions.
>    </li>
> +  <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are
> marked
> +    as deprecated. GCC will emit a warning when using the
> +    <code>-mavx5124fmaps</code>, <code>-mavx5124vnniw</code>,
> +    <code>-mavx512er</code>, <code>-mavx512pf</code>,
> +    <code>-mprefetchwt1</code>, <code>-march=knl</code>,
> +    <code>-march=knm</code>, <code>-mtune=knl</code> or <code>-
> mtune=knm</code>
> +    compiler switches. Support will be removed in GCC 15.
> +  </li>
>  </ul>
> 
>  <!-- <h3 id="mcore">MCore</h3> -->
> --
> 2.31.1
diff mbox series

Patch

diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index d3bacc16..b4b1a39a 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -543,24 +543,28 @@  You may also want to check out our
   <code>__bf16</code> type to x86 psABI. Users need to adjust their
   AVX512BF16-related source code when upgrading GCC12 to GCC13.
   </li>
-  <li>New ISA extension support for Intel AVX-IFMA was added.
-      AVX-IFMA intrinsics are available via the <code>-mavxifma</code>
+  <li>New ISA extension support for Intel AMX-COMPLEX was added.
+      AMX-COMPLEX intrinsics are available via the <code>-mamx-complex</code>
       compiler switch.
   </li>
-  <li>New ISA extension support for Intel AVX-VNNI-INT8 was added.
-      AVX-VNNI-INT8 intrinsics are available via the <code>-mavxvnniint8</code>
+  <li>New ISA extension support for Intel AMX-FP16 was added.
+      AMX-FP16 intrinsics are available via the <code>-mamx-fp16</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel AVX-IFMA was added.
+      AVX-IFMA intrinsics are available via the <code>-mavxifma</code>
       compiler switch.
   </li>
   <li>New ISA extension support for Intel AVX-NE-CONVERT was added.
       AVX-NE-CONVERT intrinsics are available via the
       <code>-mavxneconvert</code> compiler switch.
   </li>
-  <li>New ISA extension support for Intel CMPccXADD was added.
-      CMPccXADD intrinsics are available via the <code>-mcmpccxadd</code>
+  <li>New ISA extension support for Intel AVX-VNNI-INT8 was added.
+      AVX-VNNI-INT8 intrinsics are available via the <code>-mavxvnniint8</code>
       compiler switch.
   </li>
-  <li>New ISA extension support for Intel AMX-FP16 was added.
-      AMX-FP16 intrinsics are available via the <code>-mamx-fp16</code>
+  <li>New ISA extension support for Intel CMPccXADD was added.
+      CMPccXADD intrinsics are available via the <code>-mcmpccxadd</code>
       compiler switch.
   </li>
   <li>New ISA extension support for Intel PREFETCHI was added.
@@ -571,10 +575,6 @@  You may also want to check out our
       RAO-INT intrinsics are available via the <code>-mraoint</code>
       compiler switch.
   </li>
-  <li>New ISA extension support for Intel AMX-COMPLEX was added.
-      AMX-COMPLEX intrinsics are available via the <code>-mamx-complex</code>
-      compiler switch.
-  </li>
   <li>GCC now supports the Intel CPU named Raptor Lake through
     <code>-march=raptorlake</code>.
     Raptor Lake is based on Alder Lake.
@@ -585,13 +585,13 @@  You may also want to check out our
   </li>
   <li>GCC now supports the Intel CPU named Sierra Forest through
     <code>-march=sierraforest</code>.
-    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-    ENQCMD and UINTR ISA extensions.
+    Based on ISA extensions enabled on Alder Lake, the switch further enables
+    the AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPccXADD, ENQCMD and UINTR
+    ISA extensions.
   </li>
   <li>GCC now supports the Intel CPU named Grand Ridge through
     <code>-march=grandridge</code>.
-    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-    ENQCMD, UINTR and RAO-INT ISA extensions.
+    Grand Ridge is based on Sierra Forest.
   </li>
   <li>GCC now supports the Intel CPU named Emerald Rapids through
     <code>-march=emeraldrapids</code>.
@@ -599,11 +599,13 @@  You may also want to check out our
   </li>
   <li>GCC now supports the Intel CPU named Granite Rapids through
     <code>-march=graniterapids</code>.
-    The switch enables the AMX-FP16 and PREFETCHI ISA extensions.
+    Based on Sapphire Rapids, the switch further enables the AMX-FP16 and
+    PREFETCHI ISA extensions.
   </li>
   <li>GCC now supports the Intel CPU named Granite Rapids D through
     <code>-march=graniterapids-d</code>.
-    The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions.
+    Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA
+    extensions.
   </li>
   <li>GCC now supports AMD CPUs based on the <code>znver4</code> core
     via <code>-march=znver4</code>.  The switch makes GCC consider
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 24e6409a..4b83037a 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -320,8 +320,18 @@  a work-in-progress.</p>
 <h3 id="x86">IA-32/x86-64</h3>
 <ul>
   <li>New compiler option <code>-m[no-]evex512</code> was added.
-      The compiler switch enables/disables 512 bit vector and 64 bit mask
-      register. It will be default on if AVX512F is enabled.
+      The compiler switch enables/disables 512-bit vector.
+      It will be default on if AVX512F is enabled.
+  </li>
+  <li>Part of new feature support for Intel APX was added, including EGPR,
+      NDD, PPX and PUSH2POP2. APX support is available via the
+      <code>-mapxf</code> compiler switch.
+  </li>
+  <li>New ISA extension support for Intel AVX10.1 was added.
+      AVX10.1 intrinsics are available via the <code>-mavx10.1</code> or
+      <code>-mavx10.1-256</code> compiler switch with 256-bit vector size
+      support. 512-bit vector size support for AVX10.1 intrinsics are
+      available via the <code>-mavx10.1-512</code> compiler switch.
   </li>
   <li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
       AVX-VNNI-INT16 intrinsics are available via the <code>-mavxvnniint16</code>
@@ -346,13 +356,12 @@  a work-in-progress.</p>
   <li>GCC now supports the Intel CPU named Clearwater Forest through
     <code>-march=clearwaterforest</code>.
     Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
-    SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions.
-    extensions.
+    PREFETCHI, SHA512, SM3, SM4 and USER_MSR ISA extensions.
   </li>
   <li>GCC now supports the Intel CPU named Arrow Lake through
     <code>-march=arrowlake</code>.
     Based on Alder Lake, the switch further enables the AVX-IFMA,
-    AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions.
+    AVX-NE-CONVERT, AVX-VNNI-INT8 and CMPccXADD ISA extensions.
   </li>
   <li>GCC now supports the Intel CPU named Arrow Lake S through
     <code>-march=arrowlake-s</code>.
@@ -368,6 +377,14 @@  a work-in-progress.</p>
     Based on Arrow Lake S, the switch further enables the PREFETCHI ISA
     extensions.
   </li>
+  <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are marked
+    as deprecated. GCC will emit a warning when using the
+    <code>-mavx5124fmaps</code>, <code>-mavx5124vnniw</code>,
+    <code>-mavx512er</code>, <code>-mavx512pf</code>,
+    <code>-mprefetchwt1</code>, <code>-march=knl</code>,
+    <code>-march=knm</code>, <code>-mtune=knl</code> or <code>-mtune=knm</code>
+    compiler switches. Support will be removed in GCC 15.
+  </li>
 </ul>
 
 <!-- <h3 id="mcore">MCore</h3> -->