[V2] RISC-V: Enable vect test for RV32

Message ID 20231218094908.54114-1-juzhe.zhong@rivai.ai
State Committed
Commit 8c5d1d13882a0e58c308b95b1b51484721eafded
Headers
Series [V2] RISC-V: Enable vect test for RV32 |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 success Testing passed
rivoscibot/toolchain-ci-rivos-lint success Lint passed
rivoscibot/toolchain-ci-rivos-apply-patch success Patch applied
rivoscibot/toolchain-ci-rivos-build--newlib-rv64gc-lp64d-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--linux-rv64gc_zba_zbb_zbc_zbs-lp64d-non-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--linux-rv32gc_zba_zbb_zbc_zbs-ilp32d-non-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--newlib-rv64gcv-lp64d-multilib success Build passed
linaro-tcwg-bot/tcwg_gcc_check--master-aarch64 warning Patch is already merged
rivoscibot/toolchain-ci-rivos-build--linux-rv64gcv-lp64d-multilib success Build passed
linaro-tcwg-bot/tcwg_gcc_build--master-arm warning Patch is already merged
rivoscibot/toolchain-ci-rivos-test success Testing passed

Commit Message

juzhe.zhong@rivai.ai Dec. 18, 2023, 9:49 a.m. UTC
  gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add RV32.

---
 gcc/testsuite/lib/target-supports.exp | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
  

Comments

Robin Dapp Dec. 18, 2023, 10:02 a.m. UTC | #1
LGTM.

Regards
 Robin
  

Patch

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index bd38d72562d..370df10978d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11569,13 +11569,14 @@  proc check_vect_support_and_set_flags { } {
         }
     } elseif [istarget amdgcn-*-*] {
         set dg-do-what-default run
-    } elseif [istarget riscv64-*-*] {
+    } elseif [istarget riscv*-*-*] {
 	if [check_effective_target_riscv_v] {
 	    lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
 	    set dg-do-what-default run
 	} else {
-	    lappend DEFAULT_VECTCFLAGS "-march=rv64gcv_zvfh" "-mabi=lp64d"
-	    lappend DEFAULT_VECTCFLAGS "--param" "riscv-autovec-preference=scalable"
+	    foreach item [add_options_for_riscv_v ""] {
+		lappend DEFAULT_VECTCFLAGS $item
+	    }
 	    lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
 	    set dg-do-what-default compile
 	}