[v1] RISC-V: Add test case for bug PR112813
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Commit Message
From: Pan Li <pan2.li@intel.com>
The bugzilla 112813 has been fixed recently, add below test
case for the bug.
PR target/112813
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr112813-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/rvv/vsetvl/pr112813-1.c | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
Comments
LGTM Thanks.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-12-04 16:09
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test case for bug PR112813
From: Pan Li <pan2.li@intel.com>
The bugzilla 112813 has been fixed recently, add below test
case for the bug.
PR target/112813
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr112813-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/rvv/vsetvl/pr112813-1.c | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
new file mode 100644
index 00000000000..5aab9c2bf09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
@@ -0,0 +1,32 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */
+
+int a, c, d, f, j;
+int b[7];
+long e;
+char *g;
+int *h;
+long long *i;
+
+void k() {
+ int l[][1] = {{}, {1}, {1}};
+ int *m = &d, *n = &l[0][0];
+
+ for (; e;)
+ {
+ f = 3;
+
+ for (; f >= 0; f--)
+ {
+ *m &= b[f] >= 0;
+ j = a >= 2 ? 0 : 1 >> a;
+ *i |= j;
+ }
+
+ for (; c;)
+ *g = 0;
+ }
+
+ h = n;
+}
--
2.34.1
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Monday, December 4, 2023 4:10 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Add test case for bug PR112813
LGTM Thanks.
new file mode 100644
@@ -0,0 +1,32 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */
+
+int a, c, d, f, j;
+int b[7];
+long e;
+char *g;
+int *h;
+long long *i;
+
+void k() {
+ int l[][1] = {{}, {1}, {1}};
+ int *m = &d, *n = &l[0][0];
+
+ for (; e;)
+ {
+ f = 3;
+
+ for (; f >= 0; f--)
+ {
+ *m &= b[f] >= 0;
+ j = a >= 2 ? 0 : 1 >> a;
+ *i |= j;
+ }
+
+ for (; c;)
+ *g = 0;
+ }
+
+ h = n;
+}