diff mbox series

[2/2] testsuite/unroll-8: Disable vectorization for varibale-factor targets

Message ID 20231121232704.12336-5-palmer@rivosinc.com
State New
Headers
Series [1/2] testsuite/unroll-8: Avoid triggering undefined behavior |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-arm success Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-aarch64 success Testing passed

Commit Message

Palmer Dabbelt Nov. 21, 2023, 11:27 p.m. UTC 
  The vectorizer picks up these loops and disables unrolling on targets
with variable vector factors.  That result in better code here, but it
trips up the unrolling tests.  So just disable vectorization for these.

gcc/testsuite/ChangeLog:

	PR target/112531
	* gcc.dg/unroll-8.c: Disable vectorization on arm64 and riscv.
---
This also isn't tested.
---
 gcc/testsuite/gcc.dg/unroll-8.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Jeff Law Nov. 22, 2023, 10:38 p.m. UTC | #1 
On 11/21/23 16:27, Palmer Dabbelt wrote:
> The vectorizer picks up these loops and disables unrolling on targets
> with variable vector factors.  That result in better code here, but it
> trips up the unrolling tests.  So just disable vectorization for these.
> 
> gcc/testsuite/ChangeLog:
> 
> 	PR target/112531
> 	* gcc.dg/unroll-8.c: Disable vectorization on arm64 and riscv.
So probably the right check is to test for vector and 
!vect_variable_length rather than doing something target specific for 
aarch64/riscv

Jeff
Andrew Pinski Nov. 26, 2023, 4:36 a.m. UTC | #2 
On Wed, Nov 22, 2023 at 4:18 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 11/21/23 16:27, Palmer Dabbelt wrote:
> > The vectorizer picks up these loops and disables unrolling on targets
> > with variable vector factors.  That result in better code here, but it
> > trips up the unrolling tests.  So just disable vectorization for these.
> >
> > gcc/testsuite/ChangeLog:
> >
> >       PR target/112531
> >       * gcc.dg/unroll-8.c: Disable vectorization on arm64 and riscv.
> So probably the right check is to test for vector and
> !vect_variable_length rather than doing something target specific for
> aarch64/riscv

Yes I think that would definitely be better.

>
> Jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.dg/unroll-8.c b/gcc/testsuite/gcc.dg/unroll-8.c
index 06d32e56893..4465c620800 100644
--- a/gcc/testsuite/gcc.dg/unroll-8.c
+++ b/gcc/testsuite/gcc.dg/unroll-8.c
@@ -1,6 +1,15 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2 -fdump-rtl-loop2_unroll-details-blocks -funroll-loops" } */
+
+/*
+ * Targets that support variable-length vectorization don't unroll loops (see
+ * the "Disabling unrolling due to variable-length vectorization factor" out in
+ * tree-vect-loop.  So disable tree vectorization for these targets, as it will
+ * interfere with the unrolling we're looking for below.
+ */
+/* { dg-additional-options "-fno-tree-vectorize" { target aarch64-*-* } } */
 /* { dg-additional-options "-fno-tree-vectorize" { target amdgcn-*-* } } */
+/* { dg-additional-options "-fno-tree-vectorize" { target riscv*-*-* } } */
 
 struct a {int a[7];};
 void t(struct a *a, int n)