@@ -25,8 +25,8 @@ cd "$(dirname "$0")"
# Generate a header containing definitions from the string table.
gen_defines() {
cat <<EOF
-/* Generated automatically by "genstr" from "loongarch-strings".
- Please do not edit this file directly.
+/* Generated automatically by "genstr" from "loongarch-strings" and
+ "isa-evolution.in". Please do not edit this file directly.
Copyright (C) 2021-2023 Free Software Foundation, Inc.
Contributed by Loongson Ltd.
@@ -55,6 +55,15 @@ EOF
-e 's@^\([^ \t]\+\)[ \t]*\([^ \t]*\)@#define \1 "\2"@' \
loongarch-strings
+ echo
+
+ # Generate the strings from isa-evolution.in.
+ awk '{
+ a=$3
+ gsub(/-/, "_", a)
+ print("#define OPTSTR_"toupper(a)"\t\""$3"\"")
+ }' isa-evolution.in
+
echo
echo "#endif /* LOONGARCH_STR_H */"
}
@@ -77,11 +86,12 @@ gen_options() {
# print a header
cat << EOF
; Generated by "genstr" from the template "loongarch.opt.in"
-; and definitions from "loongarch-strings".
+; and definitions from "loongarch-strings" and "isa-evolution.in".
;
; Please do not edit this file directly.
; It will be automatically updated during a gcc build
-; if you change "loongarch.opt.in" or "loongarch-strings".
+; if you change "loongarch.opt.in", "loongarch-strings", or
+; "isa-evolution.in".
;
EOF
@@ -91,13 +101,85 @@ EOF
eval "echo \"$line\""
done
}
+
+ # Generate the strings from isa-evolution.in.
+ awk '{
+ print("")
+ print("m"$3)
+ gsub(/-/, "_", $3)
+ print("Target Mask(ISA_"toupper($3)") Var(isa_evolution)")
+ $1=""; $2=""; $3=""
+ sub(/^ */, "", $0)
+ print($0)
+ }' isa-evolution.in
+}
+
+gen_cpucfg_map() {
+ cat <<EOF
+/* Generated automatically by "genstr" from "isa-evolution.in".
+ Please do not edit this file directly.
+
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef LOONGARCH_CPUCFG_MAP_H
+#define LOONGARCH_CPUCFG_MAP_H
+
+#include "options.h"
+
+static constexpr struct {
+ int cpucfg_word;
+ unsigned int cpucfg_bit;
+ HOST_WIDE_INT isa_evolution_bit;
+} cpucfg_map[] = {
+EOF
+
+ # Generate the strings from isa-evolution.in.
+ awk '{
+ gsub(/-/, "_", $3)
+ print(" { "$1", 1u << "$2", OPTION_MASK_ISA_"toupper($3)" },")
+ }' isa-evolution.in
+
+ echo "};"
+ echo
+ echo "static constexpr int cpucfg_useful_idx[] = {"
+
+ awk 'BEGIN { print(" 0,\n 1,\n 2,\n 16,\n 17,\n 18,\n 19,") }
+ {if ($1+0 > max+0) max=$1; print(" "$1",")}' \
+ isa-evolution.in | sort -n | uniq
+
+ echo "};"
+ echo ""
+
+ awk 'BEGIN { max=19 }
+ { if ($1+0 > max+0) max=$1 }
+ END { print "static constexpr int N_CPUCFG_WORDS = "1+max";" }' \
+ isa-evolution.in
+
+ echo "#endif /* LOONGARCH_CPUCFG_MAP_H */"
}
main() {
case "$1" in
+ cpucfg-map) gen_cpucfg_map;;
header) gen_defines;;
opt) gen_options;;
- *) echo "Unknown Command: \"$1\". Available: header, opt"; exit 1;;
+ *) echo "Unknown Command: \"$1\". Available: cpucfg-map, header, opt"; exit 1;;
esac
}
new file mode 100644
@@ -0,0 +1,2 @@
+2 26 div32 Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+3 23 ld-seq-sa Do not need load-load barriers (dbar 0x700).
@@ -247,3 +247,10 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ
Indicate how many non memory access vector instructions can be issued per
cycle, it's used in unroll factor determination for autovectorizer. The
default value is 4.
+
+; Features added during ISA evolution. This concept is different from ISA
+; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
+; explanation. These features may be implemented and enumerated with
+; CPUCFG independantly, so we use bit flags to specify them.
+Variable
+HOST_WIDE_INT isa_evolution = 0
@@ -29,12 +29,11 @@ along with GCC; see the file COPYING3. If not see
#include "loongarch-def.h"
#include "loongarch-opts.h"
#include "loongarch-cpu.h"
+#include "loongarch-cpucfg-map.h"
#include "loongarch-str.h"
/* Native CPU detection with "cpucfg" */
-#define N_CPUCFG_WORDS 0x15
static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 };
-static const int cpucfg_useful_idx[] = {0, 1, 2, 16, 17, 18, 19};
static uint32_t
read_cpucfg_word (int wordno)
@@ -56,11 +55,8 @@ read_cpucfg_word (int wordno)
void
cache_cpucfg (void)
{
- for (unsigned int i = 0; i < sizeof (cpucfg_useful_idx) / sizeof (int); i++)
- {
- cpucfg_cache[cpucfg_useful_idx[i]]
- = read_cpucfg_word (cpucfg_useful_idx[i]);
- }
+ for (int idx: cpucfg_useful_idx)
+ cpucfg_cache[idx] = read_cpucfg_word (idx);
}
uint32_t
@@ -125,11 +121,12 @@ fill_native_cpu_config (struct loongarch_target *tgt)
int tmp;
tgt->cpu_arch = native_cpu_type;
+ auto &preset = loongarch_cpu_default_isa[tgt->cpu_arch];
+
/* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].base
With: base architecture (ARCH)
At: cpucfg_words[1][1:0] */
- #define PRESET_ARCH (loongarch_cpu_default_isa[tgt->cpu_arch].base)
switch (cpucfg_cache[1] & 0x3)
{
case 0x02:
@@ -144,19 +141,18 @@ fill_native_cpu_config (struct loongarch_target *tgt)
}
/* Check consistency with PRID presets. */
- if (native_cpu_type != CPU_NATIVE && tmp != PRESET_ARCH)
+ if (native_cpu_type != CPU_NATIVE && tmp != preset.base)
warning (0, "base architecture %qs differs from PRID preset %qs",
loongarch_isa_base_strings[tmp],
- loongarch_isa_base_strings[PRESET_ARCH]);
+ loongarch_isa_base_strings[preset.base]);
/* Use the native value anyways. */
- PRESET_ARCH = tmp;
+ preset.base = tmp;
/* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].fpu
With: FPU type (FP, FP_SP, FP_DP)
At: cpucfg_words[2][2:0] */
- #define PRESET_FPU (loongarch_cpu_default_isa[tgt->cpu_arch].fpu)
switch (cpucfg_cache[2] & 0x7)
{
case 0x07:
@@ -179,20 +175,19 @@ fill_native_cpu_config (struct loongarch_target *tgt)
}
/* Check consistency with PRID presets. */
- if (native_cpu_type != CPU_NATIVE && tmp != PRESET_FPU)
+ if (native_cpu_type != CPU_NATIVE && tmp != preset.fpu)
warning (0, "floating-point unit %qs differs from PRID preset %qs",
loongarch_isa_ext_strings[tmp],
- loongarch_isa_ext_strings[PRESET_FPU]);
+ loongarch_isa_ext_strings[preset.fpu]);
/* Use the native value anyways. */
- PRESET_FPU = tmp;
+ preset.fpu = tmp;
/* Fill: loongarch_cpu_default_isa[CPU_NATIVE].simd
With: SIMD extension type (LSX, LASX)
At: cpucfg_words[2][7:6] */
- #define PRESET_SIMD (loongarch_cpu_default_isa[tgt->cpu_arch].simd)
switch (cpucfg_cache[2] & 0xc0)
{
case 0xc0:
@@ -219,14 +214,19 @@ fill_native_cpu_config (struct loongarch_target *tgt)
/* Check consistency with PRID presets. */
/*
- if (native_cpu_type != CPU_NATIVE && tmp != PRESET_SIMD)
+ if (native_cpu_type != CPU_NATIVE && tmp != preset.simd)
warning (0, "SIMD extension %qs differs from PRID preset %qs",
loongarch_isa_ext_strings[tmp],
- loongarch_isa_ext_strings[PRESET_SIMD]);
+ loongarch_isa_ext_strings[preset.simd]);
*/
/* Use the native value anyways. */
- PRESET_SIMD = tmp;
+ preset.simd = tmp;
+
+ /* Features added during ISA evolution. */
+ for (const auto &entry: cpucfg_map)
+ if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit)
+ preset.evolution |= entry.isa_evolution_bit;
}
if (tune_native_p)
@@ -237,7 +237,7 @@ fill_native_cpu_config (struct loongarch_target *tgt)
With: cache size info
At: cpucfg_words[16:20][31:0] */
- #define PRESET_CACHE (loongarch_cpu_cache[tgt->cpu_tune])
+ auto &preset_cache = loongarch_cpu_cache[tgt->cpu_tune];
struct loongarch_cache native_cache;
int l1d_present = 0, l1u_present = 0;
int l2d_present = 0;
@@ -268,8 +268,8 @@ fill_native_cpu_config (struct loongarch_target *tgt)
>> 10; /* in kibibytes */
/* Use the native value anyways. */
- PRESET_CACHE.l1d_line_size = native_cache.l1d_line_size;
- PRESET_CACHE.l1d_size = native_cache.l1d_size;
- PRESET_CACHE.l2d_size = native_cache.l2d_size;
+ preset_cache.l1d_line_size = native_cache.l1d_line_size;
+ preset_cache.l1d_size = native_cache.l1d_size;
+ preset_cache.l2d_size = native_cache.l2d_size;
}
}
new file mode 100644
@@ -0,0 +1,48 @@
+/* Generated automatically by "genstr" from "isa-evolution.in".
+ Please do not edit this file directly.
+
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef LOONGARCH_CPUCFG_MAP_H
+#define LOONGARCH_CPUCFG_MAP_H
+
+#include "options.h"
+
+static constexpr struct {
+ int cpucfg_word;
+ unsigned int cpucfg_bit;
+ HOST_WIDE_INT isa_evolution_bit;
+} cpucfg_map[] = {
+ { 2, 1u << 26, OPTION_MASK_ISA_DIV32 },
+ { 3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA },
+};
+
+static constexpr int cpucfg_useful_idx[] = {
+ 0,
+ 1,
+ 2,
+ 3,
+ 16,
+ 17,
+ 18,
+ 19,
+};
+
+static constexpr int N_CPUCFG_WORDS = 20;
+#endif /* LOONGARCH_CPUCFG_MAP_H */
@@ -46,6 +46,7 @@ along with GCC; see the file COPYING3. If not see
#ifndef LOONGARCH_DEF_H
#define LOONGARCH_DEF_H
+#include <stdint.h>
#include "loongarch-tune.h"
#ifdef __cplusplus
@@ -121,6 +122,12 @@ struct loongarch_isa
int base; /* ISA_BASE_ */
int fpu; /* ISA_EXT_FPU_ */
int simd; /* ISA_EXT_SIMD_ */
+
+ /* ISA evolution features implied by -march=, for -march=native probed
+ via CPUCFG. The features implied by base may be not included here.
+
+ Using int64_t instead of HOST_WIDE_INT for C compatibility. */
+ int64_t evolution;
};
struct loongarch_abi
@@ -1,5 +1,5 @@
-/* Generated automatically by "genstr" from "loongarch-strings".
- Please do not edit this file directly.
+/* Generated automatically by "genstr" from "loongarch-strings" and
+ "isa-evolution.in". Please do not edit this file directly.
Copyright (C) 2021-2023 Free Software Foundation, Inc.
Contributed by Loongson Ltd.
@@ -69,4 +69,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_EXPLICIT_RELOCS_NONE "none"
#define STR_EXPLICIT_RELOCS_ALWAYS "always"
+#define OPTSTR_DIV32 "div32"
+#define OPTSTR_LD_SEQ_SA "ld-seq-sa"
+
#endif /* LOONGARCH_STR_H */
@@ -7451,6 +7451,10 @@ loongarch_option_override_internal (struct gcc_options *opts,
if (loongarch_branch_cost == 0)
loongarch_branch_cost = loongarch_cost->branch_cost;
+ /* If the user hasn't disabled a feature added during ISA evolution,
+ use the processor's default. */
+ isa_evolution |= (la_target.isa.evolution &
+ ~global_options_set.x_isa_evolution);
/* Enable sw prefetching at -O3 and higher. */
if (opts->x_flag_prefetch_loop_arrays < 0
@@ -11430,6 +11434,30 @@ loongarch_builtin_support_vector_misalignment (machine_mode mode,
is_packed);
}
+/* If -fverbose-asm, dump some info for debugging. */
+static void
+loongarch_asm_code_end (void)
+{
+#define DUMP_FEATURE(PRED) \
+ fprintf (asm_out_file, "%s %s: %s\n", ASM_COMMENT_START, #PRED, \
+ (PRED) ? "enabled" : "disabled")
+
+ if (flag_verbose_asm)
+ {
+ fprintf (asm_out_file, "\n%s CPU: %s\n", ASM_COMMENT_START,
+ loongarch_cpu_strings [la_target.cpu_arch]);
+ fprintf (asm_out_file, "%s Tune: %s\n", ASM_COMMENT_START,
+ loongarch_cpu_strings [la_target.cpu_tune]);
+ fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START,
+ loongarch_isa_base_strings [la_target.isa.base]);
+ DUMP_FEATURE (TARGET_DIV32);
+ DUMP_FEATURE (TARGET_LD_SEQ_SA);
+ }
+
+ fputs ("\n\n", asm_out_file);
+#undef DUMP_FEATURE
+}
+
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -11449,6 +11477,9 @@ loongarch_builtin_support_vector_misalignment (machine_mode mode,
#undef TARGET_ASM_FUNCTION_RODATA_SECTION
#define TARGET_ASM_FUNCTION_RODATA_SECTION loongarch_function_rodata_section
+#undef TARGET_ASM_CODE_END
+#define TARGET_ASM_CODE_END loongarch_asm_code_end
+
#undef TARGET_SCHED_INIT
#define TARGET_SCHED_INIT loongarch_sched_init
#undef TARGET_SCHED_REORDER
@@ -1,9 +1,10 @@
; Generated by "genstr" from the template "loongarch.opt.in"
-; and definitions from "loongarch-strings".
+; and definitions from "loongarch-strings" and "isa-evolution.in".
;
; Please do not edit this file directly.
; It will be automatically updated during a gcc build
-; if you change "loongarch.opt.in" or "loongarch-strings".
+; if you change "loongarch.opt.in", "loongarch-strings", or
+; "isa-evolution.in".
;
; Copyright (C) 2021-2023 Free Software Foundation, Inc.
;
@@ -254,3 +255,18 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ
Indicate how many non memory access vector instructions can be issued per
cycle, it's used in unroll factor determination for autovectorizer. The
default value is 4.
+
+; Features added during ISA evolution. This concept is different from ISA
+; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
+; explanation. These features may be implemented and enumerated with
+; CPUCFG independantly, so we use bit flags to specify them.
+Variable
+HOST_WIDE_INT isa_evolution = 0
+
+mdiv32
+Target Mask(ISA_DIV32) Var(isa_evolution)
+Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+
+mld-seq-sa
+Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution)
+Do not need load-load barriers (dbar 0x700).
@@ -18,8 +18,9 @@
GTM_H += loongarch-multilib.h
-OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \
- $(srcdir)/config/loongarch/loongarch-tune.h
+OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \
+ $(srcdir)/config/loongarch/loongarch-tune.h \
+ $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
# Canonical target triplet from config.gcc
LA_MULTIARCH_TRIPLET = $(patsubst LA_MULTIARCH_TRIPLET=%,%,$\
@@ -31,7 +32,8 @@ LA_STR_H = $(srcdir)/config/loongarch/loongarch-str.h
# String definition header
$(LA_STR_H): s-loongarch-str ; @true
s-loongarch-str: $(srcdir)/config/loongarch/genopts/genstr.sh \
- $(srcdir)/config/loongarch/genopts/loongarch-strings
+ $(srcdir)/config/loongarch/genopts/loongarch-strings \
+ $(srcdir)/config/loongarch/genopts/isa-evolution.in
$(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh header \
$(srcdir)/config/loongarch/genopts/loongarch-strings > \
tmp-loongarch-str.h
@@ -58,7 +60,8 @@ loongarch-driver.o : $(srcdir)/config/loongarch/loongarch-driver.cc $(LA_STR_H)
loongarch-opts.o: $(srcdir)/config/loongarch/loongarch-opts.cc $(LA_STR_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
-loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H)
+loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H) \
+ $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.c $(LA_STR_H)
@@ -67,6 +70,7 @@ loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.c $(LA_STR_H)
$(srcdir)/config/loongarch/loongarch.opt: s-loongarch-opt ; @true
s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
$(srcdir)/config/loongarch/genopts/loongarch.opt.in \
+ $(srcdir)/config/loongarch/genopts/isa-evolution.in \
$(srcdir)/config/loongarch/genopts/loongarch-strings $(LA_STR_H)
$(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh opt \
$(srcdir)/config/loongarch/genopts/loongarch.opt.in \
@@ -74,3 +78,12 @@ s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
$(SHELL) $(srcdir)/../move-if-change tmp-loongarch.opt \
$(srcdir)/config/loongarch/loongarch.opt
$(STAMP) s-loongarch-opt
+
+$(srcdir)/config/loongarch/loongarch-cpucfg-map.h: s-loongarch-cpucfg-map
+ @true
+s-loongarch-cpucfg-map: $(srcdir)/config/loongarch/genopts/genstr.sh \
+ $(srcdir)/config/loongarch/genopts/isa-evolution.in
+ $(SHELL) $< cpucfg-map > tmp-cpucfg.h
+ $(SHELL) $(srcdir)/../move-if-change tmp-cpucfg.h \
+ $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
+ $(STAMP) $@