diff mbox series

[V2] RISC-V: Fix bug of tuple move splitter

Message ID 20231117134800.1004906-1-juzhe.zhong@rivai.ai
State Superseded
Delegated to: Kito Cheng
Headers
Series [V2] RISC-V: Fix bug of tuple move splitter |

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Context Check Description
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Commit Message

juzhe.zhong@rivai.ai Nov. 17, 2023, 1:48 p.m. UTC 
  Fix segment fault on tuple move:

bbl loader
z  0000000000000000 ra 00000000000102ac sp 0000003ffffffaf0 gp 000000000001c0b8
tp 0000000000000000 t0 00000000000104a0 t1 000000000000000f t2 0000000000000000
s0 0000000000000000 s1 0000000000000000 a0 0000003ffffffb30 a1 0000003ffffffb58
a2 0000000000000000 a3 0000000000000000 a4 0000000000000000 a5 000000000001c340
a6 0000000000000004 a7 0000000000000004 s2 0000000000000000 s3 0000000000000000
s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
t3 0000000000000000 t4 0000000000000000 t5 0000000000000000 t6 0000000000000000
pc 00000000000101aa va/inst 0000000000000004 sr 8000000200006620
User store segfault @ 0x0000000000000004

	PR target/112561

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_tuple_move): Fix bug.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr112561.c: New test.

---
 gcc/config/riscv/riscv-v.cc                      |  2 ++
 .../gcc.target/riscv/rvv/autovec/pr112561.c      | 16 ++++++++++++++++
 2 files changed, 18 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c

Comments

Kito Cheng Nov. 18, 2023, 10:03 a.m. UTC | #1 
LGTM, and could you add one more comment before that condition: /*
Non-fractional LMUL has whole register moves that don't require a
vsetvl for VLMAX.  */

On Fri, Nov 17, 2023 at 9:48 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> Fix segment fault on tuple move:
>
> bbl loader
> z  0000000000000000 ra 00000000000102ac sp 0000003ffffffaf0 gp 000000000001c0b8
> tp 0000000000000000 t0 00000000000104a0 t1 000000000000000f t2 0000000000000000
> s0 0000000000000000 s1 0000000000000000 a0 0000003ffffffb30 a1 0000003ffffffb58
> a2 0000000000000000 a3 0000000000000000 a4 0000000000000000 a5 000000000001c340
> a6 0000000000000004 a7 0000000000000004 s2 0000000000000000 s3 0000000000000000
> s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
> s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
> t3 0000000000000000 t4 0000000000000000 t5 0000000000000000 t6 0000000000000000
> pc 00000000000101aa va/inst 0000000000000004 sr 8000000200006620
> User store segfault @ 0x0000000000000004
>
>         PR target/112561
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-v.cc (expand_tuple_move): Fix bug.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/autovec/pr112561.c: New test.
>
> ---
>  gcc/config/riscv/riscv-v.cc                      |  2 ++
>  .../gcc.target/riscv/rvv/autovec/pr112561.c      | 16 ++++++++++++++++
>  2 files changed, 18 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 6a2009ffb05..91bb6ea520d 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -2148,6 +2148,8 @@ expand_tuple_move (rtx *ops)
>           offset = ops[2];
>         }
>
> +      if (fractional_p)
> +       emit_vlmax_vsetvl (subpart_mode, ops[4]);
>        if (MEM_P (ops[1]))
>         {
>           /* Load operations.  */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
> new file mode 100644
> index 00000000000..25e61fa12c0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
> @@ -0,0 +1,16 @@
> +/* { dg-do run { target { riscv_v } } } */
> +/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */
> +
> +int printf(char *, ...);
> +int a, b, c, e;
> +short d[7][7] = {};
> +int main() {
> +  short f;
> +  c = 0;
> +  for (; c <= 6; c++) {
> +    e |= d[c][c] & 1;
> +    b &= f & 3;
> +  }
> +  printf("%d\n", a);
> +  return 0;
> +}
> --
> 2.36.3
>
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6a2009ffb05..91bb6ea520d 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2148,6 +2148,8 @@  expand_tuple_move (rtx *ops)
 	  offset = ops[2];
 	}
 
+      if (fractional_p)
+	emit_vlmax_vsetvl (subpart_mode, ops[4]);
       if (MEM_P (ops[1]))
 	{
 	  /* Load operations.  */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
new file mode 100644
index 00000000000..25e61fa12c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */
+
+int printf(char *, ...);
+int a, b, c, e;
+short d[7][7] = {};
+int main() {
+  short f;
+  c = 0;
+  for (; c <= 6; c++) {
+    e |= d[c][c] & 1;
+    b &= f & 3;
+  }
+  printf("%d\n", a);
+  return 0;
+}