RISC-V: Support RVV FP16 ZVFHMIN intrinsic API

  From: Pan Li <pan2.li@intel.com>

This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
SEW=16 for below instructions

vfwcvt.f.f.v
vfncvt.f.f.w

Then users can leverage the instrinsic APIs to perform the conversion
between RVV vector single float point and half float point.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-types.def
	(vfloat32mf2_t): Add vfloat32mf2_t type to vfncvt.f.f.w operations.
	(vfloat32m1_t): Likewise.
	(vfloat32m2_t): Likewise.
	(vfloat32m4_t): Likewise.
	(vfloat32m8_t): Likewise.
	* config/riscv/riscv-vector-builtins.def: Fix typo in comments.
	* config/riscv/vector-iterators.md: Add single to half machine
	mode conversion.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: New test.
---
 .../riscv/riscv-vector-builtins-types.def     |  6 +++
 gcc/config/riscv/riscv-vector-builtins.def    |  2 +-
 gcc/config/riscv/vector-iterators.md          | 10 ++++
 .../riscv/rvv/base/zvfhmin-intrinsic.c        | 53 +++++++++++++++++++
 4 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
  

LGTM.



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-06-04 15:19
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
From: Pan Li <pan2.li@intel.com>
 
This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
SEW=16 for below instructions
 
vfwcvt.f.f.v
vfncvt.f.f.w
 
Then users can leverage the instrinsic APIs to perform the conversion
between RVV vector single float point and half float point.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-builtins-types.def
(vfloat32mf2_t): Add vfloat32mf2_t type to vfncvt.f.f.w operations.
(vfloat32m1_t): Likewise.
(vfloat32m2_t): Likewise.
(vfloat32m4_t): Likewise.
(vfloat32m8_t): Likewise.
* config/riscv/riscv-vector-builtins.def: Fix typo in comments.
* config/riscv/vector-iterators.md: Add single to half machine
mode conversion.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: New test.
---
.../riscv/riscv-vector-builtins-types.def     |  6 +++
gcc/config/riscv/riscv-vector-builtins.def    |  2 +-
gcc/config/riscv/vector-iterators.md          | 10 ++++
.../riscv/rvv/base/zvfhmin-intrinsic.c        | 53 +++++++++++++++++++
4 files changed, 70 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
index 65716b8c637..9cb3aca992e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -553,6 +553,12 @@ DEF_RVV_WCONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_6
DEF_RVV_WCONVERT_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
DEF_RVV_WCONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
+DEF_RVV_WCONVERT_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_WCONVERT_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_WCONVERT_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_WCONVERT_F_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_WCONVERT_F_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
+
DEF_RVV_WCONVERT_F_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_WCONVERT_F_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_WCONVERT_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index 149835f36ac..310edeaf5a9 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -490,7 +490,7 @@ DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, int64, VNx16DI, VNx8DI, VOID, _i6
DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, VNx16DI, VNx8DI, VOID, _u64m8,
      _u64, _e64m8)
-/* Enabled if TARGET_VECTOR_ELEN_FP_16 && 9TARGET_ZVFH or TARGET_ZVFHMIN).  */
+/* Enabled if TARGET_VECTOR_ELEN_FP_16 && (TARGET_ZVFH or TARGET_ZVFHMIN).  */
/* LMUL = 1/4.  */
DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, VNx2HF, VNx1HF, VOID,
      _f16mf4, _f16, _e16mf4)
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 5fbaef89566..90743ed76c5 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -481,6 +481,13 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
   (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -1145,6 +1152,8 @@ (define_mode_attr V_DOUBLE_TRUNC [
   (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
   (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
   (VNx16DI "VNx16SI")
+
+  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
   (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
   (VNx16DF "VNx16SF")
])
@@ -1169,6 +1178,7 @@ (define_mode_attr v_double_trunc [
   (VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
   (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
   (VNx16DI "vnx16si")
+  (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
   (VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
   (VNx16DF "vnx16sf")
])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
new file mode 100644
index 00000000000..0923b6bc4d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_f_f_w_f16mf2(vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16mf2(src, vl);
+}
+
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16m1(src, vl);
+}
+
+vfloat16m2_t test_vfncvt_f_f_w_f16m2(vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16m2(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m1_t test_vfwcvt_f_f_v_f32m1(vfloat16mf2_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32m1(src, vl);
+}
+
+vfloat32m2_t test_vfwcvt_f_f_v_f32m2(vfloat16m1_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32m2(src, vl);
+}
+
+vfloat32m4_t test_vfwcvt_f_f_v_f32m4(vfloat16m2_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32m4(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
+
-- 
2.34.1
  

LGTM too, thanks

On Sun, Jun 4, 2023 at 3:36 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
>
> LGTM.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-04 15:19
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
> Subject: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
> From: Pan Li <pan2.li@intel.com>
>
> This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
> SEW=16 for below instructions
>
> vfwcvt.f.f.v
> vfncvt.f.f.w
>
> Then users can leverage the instrinsic APIs to perform the conversion
> between RVV vector single float point and half float point.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat32mf2_t): Add vfloat32mf2_t type to vfncvt.f.f.w operations.
> (vfloat32m1_t): Likewise.
> (vfloat32m2_t): Likewise.
> (vfloat32m4_t): Likewise.
> (vfloat32m8_t): Likewise.
> * config/riscv/riscv-vector-builtins.def: Fix typo in comments.
> * config/riscv/vector-iterators.md: Add single to half machine
> mode conversion.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: New test.
> ---
> .../riscv/riscv-vector-builtins-types.def     |  6 +++
> gcc/config/riscv/riscv-vector-builtins.def    |  2 +-
> gcc/config/riscv/vector-iterators.md          | 10 ++++
> .../riscv/rvv/base/zvfhmin-intrinsic.c        | 53 +++++++++++++++++++
> 4 files changed, 70 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 65716b8c637..9cb3aca992e 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -553,6 +553,12 @@ DEF_RVV_WCONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_6
> DEF_RVV_WCONVERT_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
> DEF_RVV_WCONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
> +DEF_RVV_WCONVERT_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_WCONVERT_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
> +DEF_RVV_WCONVERT_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
> +DEF_RVV_WCONVERT_F_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
> +DEF_RVV_WCONVERT_F_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
> +
> DEF_RVV_WCONVERT_F_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
> DEF_RVV_WCONVERT_F_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
> DEF_RVV_WCONVERT_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
> diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
> index 149835f36ac..310edeaf5a9 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -490,7 +490,7 @@ DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, int64, VNx16DI, VNx8DI, VOID, _i6
> DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, VNx16DI, VNx8DI, VOID, _u64m8,
>       _u64, _e64m8)
> -/* Enabled if TARGET_VECTOR_ELEN_FP_16 && 9TARGET_ZVFH or TARGET_ZVFHMIN).  */
> +/* Enabled if TARGET_VECTOR_ELEN_FP_16 && (TARGET_ZVFH or TARGET_ZVFHMIN).  */
> /* LMUL = 1/4.  */
> DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, VNx2HF, VNx1HF, VOID,
>       _f16mf4, _f16, _e16mf4)
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index 5fbaef89566..90743ed76c5 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -481,6 +481,13 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> +  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> +  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> +  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> +  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> +  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> +  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> +
>    (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
>    (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
>    (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
> @@ -1145,6 +1152,8 @@ (define_mode_attr V_DOUBLE_TRUNC [
>    (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
>    (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
>    (VNx16DI "VNx16SI")
> +
> +  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
>    (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
>    (VNx16DF "VNx16SF")
> ])
> @@ -1169,6 +1178,7 @@ (define_mode_attr v_double_trunc [
>    (VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
>    (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
>    (VNx16DI "vnx16si")
> +  (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
>    (VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
>    (VNx16DF "vnx16sf")
> ])
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> new file mode 100644
> index 00000000000..0923b6bc4d2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -0,0 +1,53 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
> +  return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
> +}
> +
> +vfloat16mf2_t test_vfncvt_f_f_w_f16mf2(vfloat32m1_t src, size_t vl) {
> +  return __riscv_vfncvt_f_f_w_f16mf2(src, vl);
> +}
> +
> +vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
> +  return __riscv_vfncvt_f_f_w_f16m1(src, vl);
> +}
> +
> +vfloat16m2_t test_vfncvt_f_f_w_f16m2(vfloat32m4_t src, size_t vl) {
> +  return __riscv_vfncvt_f_f_w_f16m2(src, vl);
> +}
> +
> +vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
> +  return __riscv_vfncvt_f_f_w_f16m4(src, vl);
> +}
> +
> +vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
> +  return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
> +}
> +
> +vfloat32m1_t test_vfwcvt_f_f_v_f32m1(vfloat16mf2_t src, size_t vl) {
> +  return __riscv_vfwcvt_f_f_v_f32m1(src, vl);
> +}
> +
> +vfloat32m2_t test_vfwcvt_f_f_v_f32m2(vfloat16m1_t src, size_t vl) {
> +  return __riscv_vfwcvt_f_f_v_f32m2(src, vl);
> +}
> +
> +vfloat32m4_t test_vfwcvt_f_f_v_f32m4(vfloat16m2_t src, size_t vl) {
> +  return __riscv_vfwcvt_f_f_v_f32m4(src, vl);
> +}
> +
> +vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> +  return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> +/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> +
> --
> 2.34.1
>
>
  

Committed, thanks Kito and Juzhe.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Sunday, June 4, 2023 9:38 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API

LGTM too, thanks

On Sun, Jun 4, 2023 at 3:36 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
>
> LGTM.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-04 15:19
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
> Subject: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
> From: Pan Li <pan2.li@intel.com>
>
> This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
> SEW=16 for below instructions
>
> vfwcvt.f.f.v
> vfncvt.f.f.w
>
> Then users can leverage the instrinsic APIs to perform the conversion 
> between RVV vector single float point and half float point.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat32mf2_t): Add vfloat32mf2_t type to vfncvt.f.f.w operations.
> (vfloat32m1_t): Likewise.
> (vfloat32m2_t): Likewise.
> (vfloat32m4_t): Likewise.
> (vfloat32m8_t): Likewise.
> * config/riscv/riscv-vector-builtins.def: Fix typo in comments.
> * config/riscv/vector-iterators.md: Add single to half machine mode 
> conversion.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: New test.
> ---
> .../riscv/riscv-vector-builtins-types.def     |  6 +++
> gcc/config/riscv/riscv-vector-builtins.def    |  2 +-
> gcc/config/riscv/vector-iterators.md          | 10 ++++
> .../riscv/rvv/base/zvfhmin-intrinsic.c        | 53 +++++++++++++++++++
> 4 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 65716b8c637..9cb3aca992e 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -553,6 +553,12 @@ DEF_RVV_WCONVERT_U_OPS (vuint64m2_t, 
> RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_6 DEF_RVV_WCONVERT_U_OPS 
> (vuint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64) 
> DEF_RVV_WCONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_FP_32 | 
> RVV_REQUIRE_ELEN_64)
> +DEF_RVV_WCONVERT_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
> +RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_WCONVERT_F_OPS (vfloat32m1_t, 
> +RVV_REQUIRE_ELEN_FP_32) DEF_RVV_WCONVERT_F_OPS (vfloat32m2_t, 
> +RVV_REQUIRE_ELEN_FP_32) DEF_RVV_WCONVERT_F_OPS (vfloat32m4_t, 
> +RVV_REQUIRE_ELEN_FP_32) DEF_RVV_WCONVERT_F_OPS (vfloat32m8_t, 
> +RVV_REQUIRE_ELEN_FP_32)
> +
> DEF_RVV_WCONVERT_F_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64) 
> DEF_RVV_WCONVERT_F_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) 
> DEF_RVV_WCONVERT_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) diff 
> --git a/gcc/config/riscv/riscv-vector-builtins.def 
> b/gcc/config/riscv/riscv-vector-builtins.def
> index 149835f36ac..310edeaf5a9 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -490,7 +490,7 @@ DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, 
> int64, VNx16DI, VNx8DI, VOID, _i6 DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, VNx16DI, VNx8DI, VOID, _u64m8,
>       _u64, _e64m8)
> -/* Enabled if TARGET_VECTOR_ELEN_FP_16 && 9TARGET_ZVFH or 
> TARGET_ZVFHMIN).  */
> +/* Enabled if TARGET_VECTOR_ELEN_FP_16 && (TARGET_ZVFH or 
> +TARGET_ZVFHMIN).  */
> /* LMUL = 1/4.  */
> DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, VNx2HF, VNx1HF, VOID,
>       _f16mf4, _f16, _e16mf4)
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index 5fbaef89566..90743ed76c5 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -481,6 +481,13 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> +  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")  
> + (VNx2SF "TARGET_VECTOR_ELEN_FP_32")  (VNx4SF 
> + "TARGET_VECTOR_ELEN_FP_32")  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")  
> + (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")  
> + (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> +
>    (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
>    (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
>    (VNx4DF "TARGET_VECTOR_ELEN_FP_64") @@ -1145,6 +1152,8 @@ 
> (define_mode_attr V_DOUBLE_TRUNC [
>    (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
>    (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
>    (VNx16DI "VNx16SI")
> +
> +  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF 
> + "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
>    (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
>    (VNx16DF "VNx16SF")
> ])
> @@ -1169,6 +1178,7 @@ (define_mode_attr v_double_trunc [
>    (VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
>    (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
>    (VNx16DI "vnx16si")
> +  (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF 
> + "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
>    (VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
>    (VNx16DF "vnx16sf")
> ])
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> new file mode 100644
> index 00000000000..0923b6bc4d2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -0,0 +1,53 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) 
> +{
> +  return __riscv_vfncvt_f_f_w_f16mf4(src, vl); }
> +
> +vfloat16mf2_t test_vfncvt_f_f_w_f16mf2(vfloat32m1_t src, size_t vl) {
> +  return __riscv_vfncvt_f_f_w_f16mf2(src, vl); }
> +
> +vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
> +  return __riscv_vfncvt_f_f_w_f16m1(src, vl); }
> +
> +vfloat16m2_t test_vfncvt_f_f_w_f16m2(vfloat32m4_t src, size_t vl) {
> +  return __riscv_vfncvt_f_f_w_f16m2(src, vl); }
> +
> +vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
> +  return __riscv_vfncvt_f_f_w_f16m4(src, vl); }
> +
> +vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) 
> +{
> +  return __riscv_vfwcvt_f_f_v_f32mf2(src, vl); }
> +
> +vfloat32m1_t test_vfwcvt_f_f_v_f32m1(vfloat16mf2_t src, size_t vl) {
> +  return __riscv_vfwcvt_f_f_v_f32m1(src, vl); }
> +
> +vfloat32m2_t test_vfwcvt_f_f_v_f32m2(vfloat16m1_t src, size_t vl) {
> +  return __riscv_vfwcvt_f_f_v_f32m2(src, vl); }
> +
> +vfloat32m4_t test_vfwcvt_f_f_v_f32m4(vfloat16m2_t src, size_t vl) {
> +  return __riscv_vfwcvt_f_f_v_f32m4(src, vl); }
> +
> +vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> +  return __riscv_vfwcvt_f_f_v_f32m8(src, vl); }
> +
> +/* { dg-final { scan-assembler-times 
> +{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } 
> +*/
> +/* { dg-final { scan-assembler-times 
> +{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } 
> +*/
> +/* { dg-final { scan-assembler-times 
> +{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times 
> +{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times 
> +{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times 
> +{vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> +/* { dg-final { scan-assembler-times 
> +{vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> +
> --
> 2.34.1
>
>