Message ID | 20230531092811.1269150-1-christophe.lyon@linaro.org |
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State | New |
Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 620D93858039 for <patchwork@sourceware.org>; Wed, 31 May 2023 09:28:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 620D93858039 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685525333; bh=I3Ht8CsL9DfMDvUZgQk9DzbetE52n2UajjQmRHpnY5g=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=QBXOrSdrDBkdzgd7JkDf4J89JCFROv+e4v7Nvc6uW8gZ2O9secUuSufR4EgkRinow LRiwTCMDkGtx2AbRdq0HsZVtFSBPX1jm8hsI2SW1AI9Ye9Zjl4fx78SRL4TyzqEVEU pbHtbdPteHvC2T/GyfkZdO+Y3eJWAGV+24kuLapA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oi1-x22a.google.com (mail-oi1-x22a.google.com [IPv6:2607:f8b0:4864:20::22a]) by sourceware.org (Postfix) with ESMTPS id 0E2733858D20 for <gcc-patches@gcc.gnu.org>; Wed, 31 May 2023 09:28:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0E2733858D20 Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-39a3f26688bso1151938b6e.2 for <gcc-patches@gcc.gnu.org>; Wed, 31 May 2023 02:28:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685525301; x=1688117301; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=I3Ht8CsL9DfMDvUZgQk9DzbetE52n2UajjQmRHpnY5g=; b=GMnXHIOzVL0Xh5PcoEGvYRCeIY60xH6Bzgc+/+ZnDXQuTJJW8T+IjJFpudT8i46sJI 8EiPogmVtYC20ezPp/4lhE9L6L+Jet1tqALQ0YIahtQetygsaYYclioMQXIDcDCJBUNt DK5Sb5ZZB0mhFLdwViTldEVF3TnrZSv4vL64Wrt5XLiYVS9U6N9N5/ppIM4S3gaRUZmR dNhjtPQRZ9U3fg/A2DoABOtmCgxLpCqLnOFK+4UoZ4CeYe6uxlSCVfXfrzv29WqaHRac LiGhd5uaCt3K7/D8xAu3+hWxatZJaZMj3lHTyQ7TmrmEI+Mmrqyzp4v+9MI5sEEkET4+ 9UbA== X-Gm-Message-State: AC+VfDwVf+Y9qSwx0BL6QdAKwzd93TjugVlt0tYYMNbFWCpLhMj1qO9Q 9uZiznf8ke5LZQHLirTKqmSrXHFho9ILl9iNCqpJjXN5 X-Google-Smtp-Source: ACHHUZ5kvylYT+0bDIVZZZHPxG7lVPvQxE45CwMZuaSe+XxKImXu/FKKtl3xhdkU7ZMiXFDXESXxGA== X-Received: by 2002:a05:6808:1313:b0:398:2a8a:1e02 with SMTP id y19-20020a056808131300b003982a8a1e02mr4410380oiv.45.1685525300860; Wed, 31 May 2023 02:28:20 -0700 (PDT) Received: from localhost.localdomain ([139.178.84.207]) by smtp.gmail.com with ESMTPSA id w130-20020aca6288000000b0039a016ec102sm348879oib.15.2023.05.31.02.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 May 2023 02:28:20 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com Cc: Christophe Lyon <christophe.lyon@linaro.org> Subject: [PATCH] aarch64: Add pattern for bswap + rotate [PR 110039] Date: Wed, 31 May 2023 09:28:11 +0000 Message-Id: <20230531092811.1269150-1-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Christophe Lyon <christophe.lyon@linaro.org> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
aarch64: Add pattern for bswap + rotate [PR 110039]
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Commit Message
Christophe Lyon
May 31, 2023, 9:28 a.m. UTC
After commit g:d8545fb2c71683f407bfd96706103297d4d6e27b, we missed a pattern to match the new GIMPLE form. With this patch, gcc.target/aarch64/rev16_2.c passes again. 2023-05-31 Christophe Lyon <christophe.lyon@linaro.org> PR target/110039 gcc/ * config/aarch64/aarch64.md (aarch64_rev16<mode>2_alt3): New pattern. --- gcc/config/aarch64/aarch64.md | 10 ++++++++++ 1 file changed, 10 insertions(+)
Comments
Christophe Lyon <christophe.lyon@linaro.org> writes: > After commit g:d8545fb2c71683f407bfd96706103297d4d6e27b, we missed a > pattern to match the new GIMPLE form. > > With this patch, gcc.target/aarch64/rev16_2.c passes again. > > 2023-05-31 Christophe Lyon <christophe.lyon@linaro.org> > > PR target/110039 > gcc/ > * config/aarch64/aarch64.md (aarch64_rev16<mode>2_alt3): New > pattern. > --- > gcc/config/aarch64/aarch64.md | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 8b8951d7b14..663353791fd 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -6267,6 +6267,16 @@ > [(set_attr "type" "rev")] > ) > > +;; Similar pattern to mache (rotate (bswap) 16) > +(define_insn "aarch64_rev16<mode>2_alt3" > + [(set (match_operand:GPI 0 "register_operand" "=r") > + (rotate:GPI (bswap:GPI (match_operand:GPI 1 "register_operand" "r")) > + (const_int 16)))] > + "" > + "rev16\\t%<w>0, %<w>1" > + [(set_attr "type" "rev")] > +) > + Doesn't this have to be :SI only? The rtl expression and the instruction are different for :DI. Thanks, Richard > ;; zero_extend version of above > (define_insn "*bswapsi2_uxtw" > [(set (match_operand:DI 0 "register_operand" "=r")
On Wed, 31 May 2023 at 11:49, Richard Sandiford <richard.sandiford@arm.com> wrote: > Christophe Lyon <christophe.lyon@linaro.org> writes: > > After commit g:d8545fb2c71683f407bfd96706103297d4d6e27b, we missed a > > pattern to match the new GIMPLE form. > > > > With this patch, gcc.target/aarch64/rev16_2.c passes again. > > > > 2023-05-31 Christophe Lyon <christophe.lyon@linaro.org> > > > > PR target/110039 > > gcc/ > > * config/aarch64/aarch64.md (aarch64_rev16<mode>2_alt3): New > > pattern. > > --- > > gcc/config/aarch64/aarch64.md | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/gcc/config/aarch64/aarch64.md > b/gcc/config/aarch64/aarch64.md > > index 8b8951d7b14..663353791fd 100644 > > --- a/gcc/config/aarch64/aarch64.md > > +++ b/gcc/config/aarch64/aarch64.md > > @@ -6267,6 +6267,16 @@ > > [(set_attr "type" "rev")] > > ) > > > > +;; Similar pattern to mache (rotate (bswap) 16) > > +(define_insn "aarch64_rev16<mode>2_alt3" > > + [(set (match_operand:GPI 0 "register_operand" "=r") > > + (rotate:GPI (bswap:GPI (match_operand:GPI 1 "register_operand" > "r")) > > + (const_int 16)))] > > + "" > > + "rev16\\t%<w>0, %<w>1" > > + [(set_attr "type" "rev")] > > +) > > + > > Doesn't this have to be :SI only? The rtl expression and the > instruction are different for :DI. > > Do you mean the other two examples in the testcase? ( __rev16_64_alt, __rev16_64) They currently use aarch64_rev16di2_alt1 and aarch64_rev16di2_alt2 respectively. So yeah for this case it seems :SI would be right. Thanks, Christophe Thanks, > Richard > > > ;; zero_extend version of above > > (define_insn "*bswapsi2_uxtw" > > [(set (match_operand:DI 0 "register_operand" "=r") >
Christophe Lyon <christophe.lyon@linaro.org> writes: > On Wed, 31 May 2023 at 11:49, Richard Sandiford <richard.sandiford@arm.com> > wrote: > >> Christophe Lyon <christophe.lyon@linaro.org> writes: >> > After commit g:d8545fb2c71683f407bfd96706103297d4d6e27b, we missed a >> > pattern to match the new GIMPLE form. >> > >> > With this patch, gcc.target/aarch64/rev16_2.c passes again. >> > >> > 2023-05-31 Christophe Lyon <christophe.lyon@linaro.org> >> > >> > PR target/110039 >> > gcc/ >> > * config/aarch64/aarch64.md (aarch64_rev16<mode>2_alt3): New >> > pattern. >> > --- >> > gcc/config/aarch64/aarch64.md | 10 ++++++++++ >> > 1 file changed, 10 insertions(+) >> > >> > diff --git a/gcc/config/aarch64/aarch64.md >> b/gcc/config/aarch64/aarch64.md >> > index 8b8951d7b14..663353791fd 100644 >> > --- a/gcc/config/aarch64/aarch64.md >> > +++ b/gcc/config/aarch64/aarch64.md >> > @@ -6267,6 +6267,16 @@ >> > [(set_attr "type" "rev")] >> > ) >> > >> > +;; Similar pattern to mache (rotate (bswap) 16) >> > +(define_insn "aarch64_rev16<mode>2_alt3" >> > + [(set (match_operand:GPI 0 "register_operand" "=r") >> > + (rotate:GPI (bswap:GPI (match_operand:GPI 1 "register_operand" >> "r")) >> > + (const_int 16)))] >> > + "" >> > + "rev16\\t%<w>0, %<w>1" >> > + [(set_attr "type" "rev")] >> > +) >> > + >> >> Doesn't this have to be :SI only? The rtl expression and the >> instruction are different for :DI. >> > Do you mean the other two examples in the testcase? > ( __rev16_64_alt, __rev16_64) > They currently use aarch64_rev16di2_alt1 and aarch64_rev16di2_alt2 > respectively. I meant more that the new pattern would generate wrong code if someone wrote a 64-bit bswap followed by a 64-bit rotate left. Richard
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 8b8951d7b14..663353791fd 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -6267,6 +6267,16 @@ [(set_attr "type" "rev")] ) +;; Similar pattern to mache (rotate (bswap) 16) +(define_insn "aarch64_rev16<mode>2_alt3" + [(set (match_operand:GPI 0 "register_operand" "=r") + (rotate:GPI (bswap:GPI (match_operand:GPI 1 "register_operand" "r")) + (const_int 16)))] + "" + "rev16\\t%<w>0, %<w>1" + [(set_attr "type" "rev")] +) + ;; zero_extend version of above (define_insn "*bswapsi2_uxtw" [(set (match_operand:DI 0 "register_operand" "=r")