diff mbox series

[13/26] arm: [MVE intrinsics] factorize vmvnq

Message ID 20230512093855.79529-13-christophe.lyon@arm.com
State Committed
Commit b74d6acf7366d96dee1f43667371df14a5882651
Headers
Series [01/26] arm: [MVE intrinsics] add binary_widen_opt_n shape |

Commit Message

Christophe Lyon May 12, 2023, 9:38 a.m. UTC 
  Factorize vmvnq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (mve_insn): Add vmvn.
	* config/arm/mve.md (mve_vmvnq_n_<supf><mode>): Rename into ...
	(@mve_<mve_insn>q_n_<supf><mode>): ... this.
	(mve_vmvnq_m_<supf><mode>): Rename into ...
	(@mve_<mve_insn>q_m_<supf><mode>): ... this.
	(mve_vmvnq_m_n_<supf><mode>): Rename into ...
	(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
---
 gcc/config/arm/iterators.md |  3 +++
 gcc/config/arm/mve.md       | 12 ++++++------
 2 files changed, 9 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index dfc8d9cae72..7fbfea49ff3 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1002,6 +1002,9 @@  (define_int_attr mve_insn [
 		 (VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") (VMULQ_M_N_F "vmul")
 		 (VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F "vmul")
 		 (VMULQ_N_S "vmul") (VMULQ_N_U "vmul") (VMULQ_N_F "vmul")
+		 (VMVNQ_M_N_S "vmvn") (VMVNQ_M_N_U "vmvn")
+		 (VMVNQ_M_S "vmvn") (VMVNQ_M_U "vmvn")
+		 (VMVNQ_N_S "vmvn") (VMVNQ_N_U "vmvn")
 		 (VNEGQ_M_F "vneg")
 		 (VNEGQ_M_S "vneg")
 		 (VORRQ_M_N_S "vorr") (VORRQ_M_N_U "vorr")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index beca74d4964..57ba65d3c76 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -459,14 +459,14 @@  (define_insn "mve_vcvtaq_<supf><mode>"
 ;;
 ;; [vmvnq_n_u, vmvnq_n_s])
 ;;
-(define_insn "mve_vmvnq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
   [
    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 	(unspec:MVE_5 [(match_operand:<V_elem> 1 "immediate_operand" "i")]
 	 VMVNQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vmvn.i%#<V_sz_elem>  %q0, %1"
+  "<mve_insn>.i%#<V_sz_elem>\t%q0, %1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1953,7 +1953,7 @@  (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
 ;;
 ;; [vmvnq_m_s, vmvnq_m_u])
 ;;
-(define_insn "mve_vmvnq_m_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
@@ -1962,7 +1962,7 @@  (define_insn "mve_vmvnq_m_<supf><mode>"
 	 VMVNQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmvnt %q0, %q2"
+  "vpst\;<mve_insn>t\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -2423,7 +2423,7 @@  (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
 ;;
 ;; [vmvnq_m_n_u, vmvnq_m_n_s])
 ;;
-(define_insn "mve_vmvnq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
   [
    (set (match_operand:MVE_5 0 "s_register_operand" "=w")
 	(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
@@ -2432,7 +2432,7 @@  (define_insn "mve_vmvnq_m_n_<supf><mode>"
 	 VMVNQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmvnt.i%#<V_sz_elem>	%q0, %2"
+  "vpst\;<mve_insn>t.i%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])